Now that things are setup we can simulate the reflection characteristics of these signals.
Firstly, to analyze the reflection characteristics:
- Open one of the project documents (either a schematic or the PCB)
- Run Tools » Signal Integrity
- Click the Continue button when the Errors or Warnings Found dialog pops up. This dialog opens because there are components that the Signal Integrity Analyzer cannot correctly guess a suitable model for, in this case it is a number of test points – we can ignore these as they are not part of the nets we are interested in.
- Locate the net
D0, and click the Take Over button at the top of the panel to add
D0to the right hand section of the panel.
- Make sure that the direction of the FPGA pin on this net is set to
Bi/Out, and that all other pins are set to
Bi/In. Note that the FPGA is component
U1. To change this, right click on each pin that needs to be changed, and choose Toggle In/Out to change the status. The reason for this is that we want the FPGA pin to be driving the net for the signal integrity analysis.
- Click the Reflections button at the bottom of the panel to run a Reflection Analysis on the net
D0. The resulting waveform will appear, as shown in Figure 2.
- Locate the signal
D0in the FPGA Signal Manager dialog and set the Slew Rate to the
FASToption. Click OK and then execute the subsequent engineering change order that is generated. The associated constraint file will be updated with the new setting and opened as the active document. Save and close this file.
- Display the Signal Integrity panel again (you can click the button down the bottom of the workspace if you closed the panel), and click the Reanalyze Design button.
- Ensure that the FPGA pin is still set to be the output pin on the net (
Bi/Out). Then run a reflection analysis on
D0again and note that there is now some ringing on this signal (Figure 3).
So just how much ringing can we allow on these signals in order to avoid glitches on the input pins? Consulting the datasheets for components
U9 reveals the following characteristics:
- Maximum VIL =
- Min VIH =
NBP-28.sdf waveform document you will find Charts for a range of possible Slew and Drive Strength settings. There is also a chart named "Comparison" with all the different waveforms combined for comparison . To scroll through the different waves, select a wave name and use the mouse scroll wheel or up down arrows.
The comparison graph was generated using the File » Export » Chart command to create a CSV file for each of the charts. The wave names were changed inside this file to follow the above convention, and then the CSV files were all imported into a new chart.
From browsing these waveforms we can see that most of the FAST slew rate waveforms are not acceptable as they have excessive ringing present on the signals. With the slew rate set to
6mA drive strength gives the cleanest looking waveform (Figure 4).
A drive strength of
8mA would probably be acceptable although there is some ringing (Figure 5).
Any drive strengths above this generate large amounts of ringing, particularly on
87 (Figure 6).
You can see from the waveforms that the slew rate and drive strengths can have a huge effect on how clean the signals are. By modifying the slew and drive characteristics we can select values that provide a suitably fast and clean response.
Given the above findings we would select
SLOW slew rate and
6mA drive strength for the FPGA pins. We would definitely not want to drive it any harder than
8mA or use the
FAST slew rate setting without adding terminations on the PCB.
SLOW Slew and
6mA drive strength for all the FPGA signals D[31..0] in the signal manager we can now verify that this gives satisfactory waveforms for all these signals.
- Make these changes in the FPGA Signal Manager dialog.
- Re-analyze the design with the Signal Integrity tool.
- Take across signal D[31..0]
- Remember to check the i/o direction of the pins, make sure that for each signal the FPGA pins are set to
Bi/Outand all other pins are
- Click the Reflections button. This generates a chart of reflection waveforms for each of the selected signals.
Examining the generated waveforms shows that
6mA drive strength gives acceptable waveforms for all these signals.
If we wanted to drive the pins harder than this then it would be necessary to place terminations on the PCB. The termination advisor is a useful tool for deciding upon a type of termination to use, and it can be used to sweep values of termination components across a range.
Using the termination advisor:
- Using the FPGA Signal Manager dialog, set the drive current for
- Re-analyze the design with the Signal Integrity tool
- Take across signal
- Make sure that the FPGA pin
AA17is set to
Bi/Out, and all other pins are set to
- Enable all the different termination types.
- Un-check the Perform Sweep checkbox.
- Click the Reflections button, and waves will be generated for each termination type.
- From the results we can see that a serial resistor looks like it will fix the ringing.
- In the Signal Integrity panel, disable all terminations except for Serial Resistor.
- Check the Perform Sweep option.
- Click the Reflections button.
- Click on the name of the first wave in the legend, and use the mouse wheel to scroll through the waves for different termination resistance values. It would appear that a value around
47 Ohmswould work well, so lets perform a reflection simulation with this value.
- Uncheck the Perform Sweep option.
- Change the value of the Serial Resistor to
- Run the reflection analysis.
As you can see, this can be a useful tool for selecting terminations in order to solve SI issues. The values used for each sweep are shown in the waveform hint for each wave. In the above example we can see that a value of
47 ohms for the serial resistor should provide a good termination if we needed to use the high drive current option for the FPGA output pin. In
NBP-28.sdf there is a chart named
Comparison2. This contains a comparison of the
24mA drive current terminated with a
47 Ohm serial resistor with the
6mA drive current waveforms (Figure 7).
There is not much difference between these signals, so unless we needed the higher drive current we are best off sticking to the
6mA and avoiding the need to add termination resistors.