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Now that things are setup we can simulate the reflection characteristics of these signals.

Firstly, to analyze the reflection characteristics:

  1. Open one of the project documents (either a schematic or the PCB)
  2. Run Tools » Signal Integrity
  3. Click the Continue button when the Errors or Warnings Found dialog pops up. This dialog opens because there are components that the Signal Integrity Analyzer cannot correctly guess a suitable model for, in this case it is a number of test points – we can ignore these as they are not part of the nets we are interested in.

    The design will be analyzed and the Signal Integrity panel will open, listing all the nets in the design. What has happened is that a fast analysis has been performed on all nets in the design, called a screening analysis, with the results being listed down the left side of the Signal Integrity panel. Screening is used to quickly identify potential problem nets, which can then be analyzed in more detail. To analyze a net in more detail it is taken over to the right hand side of the panel, where a reflection or cross talk analysis can be performed. Note that a number of nets have a status of Not Analyzed, typically this is because these nets include a connector pin.

    As part of the screening analysis results, you will see that failed nets have red backgrounds to their cells. For Overshoot and Undershoot conditions, the Signal Integrity engine has built-in thresholds that it can test against. These are configured in the Set Screening Analysis Tolerances dialog. Access this dialog by clicking on the Menu button and choosing the Set Tolerances command.

  4. Locate the net D0, and click the Take Over button at the top of the panel to add D0 to the right hand section of the panel.
  5. Make sure that the direction of the FPGA pin on this net is set to Bi/Out, and that all other pins are set to Bi/In. Note that the FPGA is component U1. To change this, right click on each pin that needs to be changed, and choose Toggle In/Out to change the status. The reason for this is that we want the FPGA pin to be driving the net for the signal integrity analysis.

    Figure 1. Set the FPGA pin to Bi/Out and the rest of the pins in the net to Bi/In.
  6. Click the Reflections button at the bottom of the panel to run a Reflection Analysis on the net D0. The resulting waveform will appear, as shown in Figure 2.

    Figure 2. Waveform for D0 at the FPGA pin, with Slew = SLOW and Drive = 4mA.
  7. Locate the signal D0 in the FPGA Signal Manager dialog and set the Slew Rate to the FAST option. Click OK and then execute the subsequent engineering change order that is generated. The associated constraint file will be updated with the new setting and opened as the active document. Save and close this file.
  8. Display the Signal Integrity panel again (you can click the button down the bottom of the workspace if you closed the panel), and click the Reanalyze Design button.
  9. Ensure that the FPGA pin is still set to be the output pin on the net (Bi/Out). Then run a reflection analysis on D0 again and note that there is now some ringing on this signal (Figure 3).

    Figure 3. Waveform for D0 at the FPGA pin, with Slew = FAST and Drive = 4mA.

So just how much ringing can we allow on these signals in order to avoid glitches on the input pins? Consulting the datasheets for components U5, U7 and U9 reveals the following characteristics:

  • Maximum VIL = 0.8
  • Min VIH = 2.0

In the NBP-28.sdf waveform document you will find Charts for a range of possible Slew and Drive Strength settings. There is also a chart named "Comparison" with all the different waveforms combined for comparison . To scroll through the different waves, select a wave name and use the mouse scroll wheel or up down arrows.

The naming of the waveform in the comparison follows the following format:
<signal><comp designator>.<pin><slew>_<drive>
For example D0_U1.AA17_F_6mA is the waveform for signal D0, component U1, pin AA17, Fast slew rate, 6mA drive strength.

The comparison graph was generated using the File » Export » Chart command to create a CSV file for each of the charts. The wave names were changed inside this file to follow the above convention, and then the CSV files were all imported into a new chart.

From browsing these waveforms we can see that most of the FAST slew rate waveforms are not acceptable as they have excessive ringing present on the signals. With the slew rate set to SLOW, 6mA drive strength gives the cleanest looking waveform (Figure 4).

Figure 4. Waveform for D0 at the FPGA and Processor pins, with Slew = SLOW and Drive = 6mA.

A drive strength of 8mA would probably be acceptable although there is some ringing (Figure 5).

Figure 5. Waveform for D0 at the FPGA and Processor pins, with Slew = SLOW and Drive = 8mA.

Any drive strengths above this generate large amounts of ringing, particularly on U5, pin 87 (Figure 6).

Figure 6. Waveform for D0 at the FPGA and Processor pins, with Slew = SLOW and Drive = 12mA.

You can see from the waveforms that the slew rate and drive strengths can have a huge effect on how clean the signals are. By modifying the slew and drive characteristics we can select values that provide a suitably fast and clean response.

Given the above findings we would select SLOW slew rate and 6mA drive strength for the FPGA pins. We would definitely not want to drive it any harder than 8mA or use the FAST slew rate setting without adding terminations on the PCB.

Selecting SLOW Slew and 6mA drive strength for all the FPGA signals D[31..0] in the signal manager we can now verify that this gives satisfactory waveforms for all these signals.

  1. Make these changes in the FPGA Signal Manager dialog.
  2. Re-analyze the design with the Signal Integrity tool.
  3. Take across signal D[31..0]
  4. Remember to check the i/o direction of the pins, make sure that for each signal the FPGA pins are set to Bi/Out and all other pins are Bi/In.
  5. Click the Reflections button. This generates a chart of reflection waveforms for each of the selected signals.

Examining the generated waveforms shows that 6mA drive strength gives acceptable waveforms for all these signals.

If we wanted to drive the pins harder than this then it would be necessary to place terminations on the PCB. The termination advisor is a useful tool for deciding upon a type of termination to use, and it can be used to sweep values of termination components across a range.

Using the termination advisor:

  1. Using the FPGA Signal Manager dialog, set the drive current for D0 to 24mA.
  2. Re-analyze the design with the Signal Integrity tool
  3. Take across signal D0.
  4. Make sure that the FPGA pin AA17 is set to Bi/Out, and all other pins are set to input.
  5. Enable all the different termination types.
  6. Un-check the Perform Sweep checkbox.
  7. Click the Reflections button, and waves will be generated for each termination type.
  8. From the results we can see that a serial resistor looks like it will fix the ringing.
  9. In the Signal Integrity panel, disable all terminations except for Serial Resistor.
  10. Check the Perform Sweep option.
  11. Click the Reflections button.
  12. Click on the name of the first wave in the legend, and use the mouse wheel to scroll through the waves for different termination resistance values. It would appear that a value around 47 Ohms would work well, so lets perform a reflection simulation with this value.
  13. Uncheck the Perform Sweep option.
  14. Change the value of the Serial Resistor to 47.
  15. Run the reflection analysis.

As you can see, this can be a useful tool for selecting terminations in order to solve SI issues. The values used for each sweep are shown in the waveform hint for each wave. In the above example we can see that a value of 47 ohms for the serial resistor should provide a good termination if we needed to use the high drive current option for the FPGA output pin. In NBP-28.sdf there is a chart named Comparison2. This contains a comparison of the 24mA drive current terminated with a 47 Ohm serial resistor with the 6mA drive current waveforms (Figure 7).

Figure 7. Waveform for D0 at the FPGA pin, with Slew = SLOW, Drive = 24mA and 47Ohm Series Resistor.

There is not much difference between these signals, so unless we needed the higher drive current we are best off sticking to the 6mA and avoiding the need to add termination resistors.

See Also

  • None