Altium Wiki

Information and resources for electronic product designers

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0-9

Page: 1-Wire Overview
The 1-Wire bus protocol defines a simple serial communications scheme between a single master and one or more slave devices – all of which interface to the bus using a single data line (Figure 1). Figure 1. Simplified diagram of the 1-Wire concept. The si
Page: 32-bit VGA Controllers - Accessing Shared Memory
If the same physical memory device is used for both processing code and video data storage, connection to the memory should be made through an appropriately configured bus arbitration component: On an OpenBus System Document – an Arbiter component. On a S
Page: 32-bit VGA Controllers - Host to Controller Communications
Communications between a 32-bit host processor and a 32-bit VGA Controller are carried out over a standard Wishbone bus interface. The following sections detail the communication cycles involved, where applicable, between host and Controller for writing t
Page: 32-bit VGA Controllers - Timing Information
The following tables provide information for setting the internal timing registers (HTIM and VTIM), when using either the VGA32 or VGA32_16BPP variants of 32-bit VGA Controller. Timing values are based on a variety of different monitor resolutions and ref
Page: 3D Body
Description A 3D body is a primitive polygon type design object that can be placed into a library component footprint or PCB document, on any enabled mechanical layer. It can be used to specifically define the physical size and shape of a component - both
Page: 3D Body Conversion to Generic STEP Model
Japanese Altium Designer's PCB Editor supports both 2-dimensional and 3-dimensional PCB design, with full component clearance checking in 3 dimensions. To accurately represent the loaded board in 3D, each component must be modeled in 3 dimensions. Compone
Page: 3D Single Layer Mode
3D Single Layer Mode  3D Single Layer Mode PCB Visualization in the 3D arena has been enhanced in this release, with the provision of single layer mode - particularly useful when inspecting internal power planes. Operation of single layer mode when viewin
Page: 3D Visualization Panel
3D Visualization Panel Relative position in 2D design editor window Relative position in 3D design editor window Function The 3D Visualization panel displays up to three simultaneous 3D views including cross-sections and a floating Board Insight. Using th

A

Page: A 32-bit Processor's Physical Interface to Memory and Peripherals
For each of the supported 32-bit processors available with Altium Designer, the physical interface to the outside world is always 32 bits wide. Since the addressing has a byte-level resolution, this means that up to four "packets" of data (bytes) can be l
Page: A Tour of the Scripting System
The scripting system in Altium Designer gives you the ability to create and run scripts to automate specific tasks. Altium Designer's script editor, debugger and scripting panels work together to help you write and debug your scripts easily. Figure 1: Alt
Page: A Walk Through...Altium's Vault-Driven Electronics Design Methodology
Altium の Vault によるエレクトロニクス設計の方法 Designing with Altium mini-site An Introduction to Vault-Driven Electronics Design Getting Started with the Vault-driven Methodology Parent article: Vault-Driven Electronics Design Using its own unified electronic product d
Page: A Walk Through...Installing Altium Designer with the Altium Platform Installer
Altium プラットフォームインストーラで Altium Designer をインストール Altium Designer - Installation and Management Parent article: Installation and Content Management Installation of any software application should be straightforward, intuitive and, perhaps above all, fast – y
Page: A Walk Through...Migrating from a Satellite Vault to an Altium Vault Server or Personal Vault
Satellite Vault から Altium Vault Server、または Personal Vault へ移行   The Altium Satellite Vault Server (or 'Satellite Vault') has been the faithful, sole offering of Altium's Vault Technology since the latter's inception, and the foundational cornerstone of Al
Page: A Walk Through...Post-Installation Management of your Altium Designer Solution
Altium Designer インストール後の管理 Altium Designer - Installation and Management Parent article: Installation and Content Management Altium Designer's Installation Management System allows you to essentially handcraft your installation of the software at any time
Page: A Walk Through...Releasing a Simulation Model Definition to an Altium Vault
Simulation Model 定義を Altium Vault へリリース   Related article: Adding a Simulation Model to a Component Definition From a designer's perspective, a vault-based component gathers together all information needed to represent that component across all design dom
Page: A Walk Through...the Board Design Release Process
Japanese Parent article: Vault-Driven Electronics Design Altium's Design Data Management system includes a range of technologies that combine together to allow you to pass data from the design domain to the production domain in a pain-free, streamlined, a
Page: A Word about Changing Daughter Boards
Figure 1. Switch daughter boards to change the target architecture. When changing FPGA daughter boards, please take care not to damage the connectors that attach the daughter board to the NB2DSK01. The following procedure is recommended: Ensure that the N
Page: A Word on Connecting External Memory...
When connecting to physical memory outside of the FPGA device, the wiring involved will depend on the type of memory and where it is located. If the memory is located on a NanoBoard or a plug-in daughter board, simply place the appropriately-configured Me
Page: Ability to Disable Via Pushing when Interactively Routing
Japanese Enhanced Routing Capabilities Altium Designer already supported the ability to push vias as you interactively route your board, available while routing in one of the push-based routing modes – Push Obstacles or Hug and Push Obstacles. However, th
Page: Ability to Push Vias when Interactively Routing
Japanese In the Winter 10 release of Altium Designer, you can now push vias out of your way as you route your board using the Interactive Router. A via will only be pushed if there is space to do so, and the new location does not violate defined clearance
Page: Ability to Rename Lifecycle Definition and Item Revision Naming Schemes
ライフサイクル定義と Item Revision Naming Scheme の名称を変更する機能   Previously, when a defined Lifecycle Definition or Revision Naming Scheme became used by an Item in the Altium Vault, that scheme could no longer be edited (nor could it be deleted for that matter). But
Page: Ability to send a Crash Report
Japanese Altium Designer provides you with the ability to send a crash report through to the Altium Developers, should you encounter an error in the software. In the error/exception dialog that appears, simply click the Send Report button and add a descri
Page: Ability to Set ID for Initial Revision of a Vault Item
Vault Item の最初のレビジョンの ID を設定する機能   Changing from an unmanaged design paradigm to a vault-centric managed one, requires migrating existing data to an Altium Vault. Such data may well have passed through multiple iterations and revision numbering assigned t
Page: Accelerating Processor Systems
In many processor systems, the embedded processor is charged with handling computationally-intensive algorithms. These algorithms place a burden on the processor, which can have a significant impact on intended performance. The performance of such designs
Page: Accessing and Using Power Monitoring
Prior to accessing the power monitoring in Altium Designer, ensure that the Desktop NanoBoard is connected to the PC (via USB or Parallel connection) and is powered-on. 'Command Central' for power monitoring can be found on the instrument panel for the Na
Page: Accessing Common-Bus Memory on a 3-Connector Daughter Board
Table 1 summarizes the available design interface components that can be placed from the FPGA DB Common Port-Plugin.IntLib for access to, and communications with, any or all of the common-bus memory resources on a 3-connector daughter board. Table 1. Comm
Page: Accessing Common-Bus Resources on the NanoBoard 3000
The following resources resident on a 3000-series NanoBoard share a common data bus, address bus and read and write enable lines: Common-bus SRAM Common-bus SDRAM Common-bus Flash memory USB Hub (more specifically, the ISP1760 Hi-speed USB Host Controller
Page: Accessing NanoBoard Resources from an FPGA Design
Related articles: NanoBoard NB2 Motherboard Resources, NanoBoard 3000 - Motherboard Resources Normally you would use ports to connect from the nets in a design to the pins on the FPGA. However, since the connectivity from the FPGA to resources is fixed by
Page: Accessing Peripheral Board Resources
Resources on the plug-in peripheral boards are made available to the physical FPGA device on the currently attached daughter board. The corresponding I/O pins from each peripheral board connector – 50 each – are wired directly to pins of the daughter boar
Page: Accessing SPI Flash Memory Attached to a Processor
Japanese 访问绑定于处理器的SPI 总线Flash存储器 The NanoBoard NB2 and 3000-series NanoBoards all feature SPI Flash memory that can be programmed with a design for boot purposes – downloading that stored design to the User FPGA when the board is powered. Getting your des
Page: Accessing System Resources
Japanese Access to system resources has been given a makeover, with the arrival of a new pop-out style panel that replaces the DXP menu in releases of old. This panel is accessed by clicking on the button, in the top-left corner of the application window.
Page: Accessing the Custom Instrument's Run-time Panel
The host computer is connected to a target Custom Instrument using the IEEE 1149.1 (JTAG) standard interface. This is the physical interface, providing connection to physical pins of the FPGA device in which the instrument has been embedded. The Nexus 500
Page: Accessing the Embedded Debug Environment
How do I debug my design? How do I navigate around my source code? Debugging of the embedded code within a 32-bit processor is carried out by starting a debug session. Prior to starting the session, you must ensure that the design, including one or more d
Page: Accessing Unused Data Pins of the Parallel Port
Communication over both Hard Devices and Soft Devices JTAG chains simultaneously is not supported. Where use of both channels has been defined – in the associated JTAG Board file – a channel needs to be initialized (prior to using it) and then finalized (
Page: Accessing Virtual Instruments at Runtime
How do I build an FPGA design? Before looking at the instruments themselves, it is worth taking the time to see how instruments are accessed from within Altium Designer and the underlying communications scheme that makes this possible. Communications from
Page: Actel CoreMP7
Figure 1. CoreMP7 32-bit processor. Altium Designer's CoreMP7 component is a 32-bit Wishbone-compatible RISC processor, for use in FPGA designs targeting supported Actel Fusion or ProASIC®3 families of physical FPGA devices.   Altium Designer supports use
Page: ActiveBOM
ActiveBOM   Facilitating real-time cost estimation and tracking for a board design, Altium Designer brings to the table a system that effectively and efficiently aides the designer in managing costs and availability of items used in that design. This syst
Page: ActiveBOM - BOM Catalog
Parent article: ActiveBOM The BOM Catalog tab is a constituent part of the BOM document (*.BomDoc), and essentially the 'nerve center' of the ActiveBOM concept. It is here that you can: Browse a listing of all items actually used in the design. Add additi
Page: ActiveBOM - BOM Components
Parent article: ActiveBOM The BOM Components tab is a constituent part of the BOM document (*.BomDoc), and a key structural element in the ActiveBOM concept. It presents the BOM itself – a listing of all instances of components used in the design (core ca
Page: ActiveBOM - FAQs
ActiveBOM - FAQs Working with the BOM Catalog Tab Working with the BOM Components Tab The following links provide quick access to pertinent areas within the documentation available for ActiveBOM: Accessing the BOM Document Sourcing Supplier Data Working w
Page: Acute Angle
Creating Design Rules Design Rules Rule Category: Manufacturing Description Specifies the minimum angle permitted between any objects in the same net. The Acute Angle rule works on nets only. It finds all the acute angles created by any objects in one net
Page: Adding a Secondary (Redundant) Private License Server
Main article: Using a Private Server License The Private License Server supports setting up a redundant Secondary license server. This server does not respond to a license request from a Client unless the Primary server is no longer available on the netwo
Page: Adding a Simulation Model to a Component Definition
シミュレーションモデルをコンポーネント定義へ追加   Related article: A Walk Through...Releasing a Simulation Model Definition to an Altium Vault On the design side, each design component released to an Altium Vault is specified using a source Component Definition. A component def
Page: Adding Assembly Variants
The controls for adding, defining and removing assembly variants for a design can be found in the Assembly Variant Management dialog, accessed by choosing Assembly Variants from the Project menu. A new assembly variant can be added either by clicking on t
Page: Adding Design Rule Directives to a Schematic Document
Design constraints (rules) can be defined prior to PCB layout, by adding parameters that are configured as design rule directives to the schematic source document(s). The scope of the corresponding PCB design rule, created when the design is transferred t
Page: Adding Output Generators
When you create a new Output Job file, only the relevant output generators are added to the file and configured using default setups. To quickly clear these output generators and start with a 'blank canvas', press CTRL + A , followed by DELETE . A dialog
Page: Adding Schematic-based Devices to an OpenBus System Design
Building the main processor system solely within the self-contained walls of the OpenBus System document will be an attractive solution for the majority of designs. However, you may need (or even want) to separate certain devices from the system, and have
Page: Additional Output Generators
Additional output generators allow you to further streamline and automate the design release process. In particular, the inclusion of ERC and DRC Report Output Generators which constitute a powerful enhancement to the OutputJob document. ERC Report Output
Page: Additional Output Publishers
The main role of the new web publisher output medium is to enhance collaboration by making web publication of design outputs (graphical and table based) easy and automatable. The new web publisher will publish the outputs of Outjob Documents on web hosted
Page: Additional Schematic Power Objects
追加された回路図のパワーオブジェクト   The release of Altium Designer 13.3 brings 4 new styles of Power Port to the Schematic Editor. These symbols have been created to allow designers to comply with the GOST standards, a set of technical standards maintained by the Euro-A
Page: Address Decode Bits Vs Base Address - a Juggling Act
When specifying the Decode Address Width, you should try to set the number of address decode bits to a value that will adequately cover the number of slave devices you wish to link to the Interconnect component. The simple approach is to take the number o
Page: Advanced Search Syntax
Here's how you can refine your search. The Altium Wiki will ignore common words like "the" unless you place your query within quotes. Exact phrase search To search for content that contains the exact phrase "chalk and cheese" "chalk and cheese" Or Search
Page: ALDC standards
The Altium Library Development Center operates under strict procedures designed to ensure the quality and integrity of all libraries and the components they contain. PCB footprints - surface mount PCB footprints for surface mount packages are built to the
Page: Altera Nios II
Figure 1. Nios II 32-bit processor. The Nios II is a 32-bit Wishbone-compatible RISC processor, for use in FPGA designs targeting supported Altera families of physical FPGA devices.   Altium Designer currently supports use of the Nios II processor with th
Page: Altera Place and Route Tools Configuration
The place and route tools are all accessed and configured from the Build stage of the Process Flow associated to the target physical device in the Devices view. To enable and display the Process Flow when the target device is an Altera FPGA you must: Have
Page: Altera Quartus II Synthesizer Configuration
The system includes a powerful built-in synthesis engine, which is used by default. It also supports use of the Altera Quartus II synthesizer within the design environment. To enable an FPGA project to utilize this synthesis tool the project synthesis opt
Page: Altium Agreements
Altium の許諾契約   Altium End-User License Agreement All Altium software products are covered by the terms of the End-User License Agreement (EULA). Before using the Altium software product, please read the EULA carefully. By using the product you are agreein
Page: Altium Content Vault
Altium Content Vault   In previous versions of Altium Designer, the designer could connect to Altium's own vaults – vaults that were part of the AltiumLive ecosystem, and to which the designer had authenticated access (i.e. a licensed instance of Altium D
Page: Altium Designer
Altium Designer 統一設計環境: Altium Designer Altium Designer What's New in Altium Designer — Find out about new features and enhancements in recent releases of Altium Designer. Getting Started — A collection of links to articles and videos about getting starte
Page: Altium Designer 10 - FAQs
This section is intended to cover common questions about installing your Altium Designer 10 package. Where can I find information for installing Altium Designer 10? A Walk Through...Installing Altium Designer with the Altium Platform Installer Note: To in
Page: Altium Designer 10 Release Notes (10.759.23105)
To be forwarded to the release notes for Altium Designer 10 Update 14, please click here: Release notes for Altium Designer 10 Update 14 (10.771.23139)
Page: Altium Designer 2004 - Service Pack 1
Altium Designer 2004 SP1 highlights include significant updates to Protel’s autorouting technology, and the addition of Spartan-3 device support to Nexar. The following list presents a complete list of updates and enhancements made for Service Pack 1 for
Page: Altium Designer 2004 - Service Pack 2
Service Pack 2 includes more than 150 new features and enhancements, as well as over 100 updates to the Altium Designer solution. For this service pack we have worked closely with designers using Altium Designer as we tuned and enhanced the software, with
Page: Altium Designer 2004 - Service Pack 3
With Service Pack 3, we've introduced the Altium Designer name to represent the single, unified system built on our unique DXP technology integration platform. Your Altium Designer DXP-based license provides access to a targeted set of Altium Designer's f
Page: Altium Designer 2004 - Service Pack 4
Altium Designer 2004 Service Pack 4 includes over 100 new features and enhancements that will save you time and improve your work flows. Highlights include: Improved design team support with the new file locking option. With this option enabled files are
Page: Altium Designer 2004 - Software Updates
Service Packs Service Pack 4 (Build Number 8.4.03.3664)is the latest release of Altium Designer. We recommend that you update your software to this latest version to have all the new features, enhancements and improvements. IMPORTANT NOTE: Service Pack 4
Page: Altium Designer 2004 Libraries
Altium Designer board-level design integrated libraries Browse, search and download up-to-date Altium Designer 2004 integrated libraries for board-level design, which include 79,782 components. The below library downloads are deemed to be 'frozen librarie
Page: Altium Designer 6 - Downloads
Downloads There are now three ways to update Altium Designer. 1. Web updates from within Altium Designer Altium Designer 6 includes the ability to check for, download or automatically install updates from within the Altium Designer software. This is confi
Page: Altium Designer 6 - Local Update Server Setup
Altium Designer has the ability to check Altium’s server for available software updates. Information on other ways of updating Altium Designer 6 can be found on the Altium Designer 6 - Downloads page. Alternatively, updates can be downloaded and stored on
Page: Altium Designer 6 - Release Info Container
Page: Altium Designer 6 - Release Notes
Altium Designer 6.8 web update - Released November 2007 Altium Designer 6.8 release notes Altium Designer 6.7 web update - Released March 2007 Altium Designer 6.7 release notes Altium Designer 6.6 web update - Released November 2006 Altium Designer 6.6 re
Page: Altium Designer 6 - Release Notes Beta
Release notes for Altium Designer 6.0 Production Build 6.0.0.5208 Miscellaneous fixes PCB Shift+W popup is now shown in the proper size Interactive routing TAB dialog - popup menu now appears in the correct location Foundation licenses can no longer updat
Page: Altium Designer 6 - Software Updates
Software updates for Altium Designer 6. Self-contained updates These updates can only be applied to an existing Altium Designer 6 installation. Updates are non-cumulative meaning that before any update can be installed, the version immediately prior to it
Page: Altium Designer 6.0
Altium Designer 6.9 web update Altium continues to deliver electronics design tools that break the mould, with the latest release – Altium Designer 6.9. Altium Designer 6.9 takes Altium Designer 6.8 one step further, building on market-leading features su
Page: Altium Designer 6.0.1 Release Notes
List of updates for Build No. 6.0.1.5229 Resolved software crash that occurred under certain conditions while selecting a part in the component properties dialog. This crash occurred when clicking the 'Choose' button in the component properties dialog, if
Page: Altium Designer 6.0.2 Release Notes
Altium Designer 6.0.2.5495 PCB The PCB DRC has been improved. Allow Short Circuit constraints no longer cause incorrect violation counts. Fixed problem with opening multiple html report documents The robustness of Component Classes in the PCB editor has b
Page: Altium Designer 6.3 Release Notes
Build 6.3.6641 PCB Major fixes in the Align / Arrange commands The behavior of Place Rectangular Room command has been improved. Now the mouse cursor snaps to the closest vertex of the room. Now any of these commands work even after undoing the Align comm
Page: Altium Designer 6.4 Release Notes
Build 6.4.0.7263 PCB Octagonal pads are now rendered correctly when using Direct X graphics. Multi-trace routing now displays connection lines. Multi-trace route finishing angle, as toggled by '\' key, is now relative to the last tracks rather than absolu
Page: Altium Designer 6.5 Release Notes
Build 6.5.7356 PCB Vias and multi-layer pads are now exported correctly to DXF. When using Interactive Routing and other interactive process in DirectX mode, pads will no longer be partially erased when the mouse cursor moves or the HeadsUp display is in
Page: Altium Designer 6.6 Release Notes
Build 6.6.7903 PCB When drawing tracks in masked state, their net names remained distractingly bright. Net names are now dimmed consistently with their masked tracks. The polygon manager has been improved and now correctly remembers grid settings includin
Page: Altium Designer 6.7 Release Notes
Build 6.7.0.9346 PCB IPC Footprint Wizard now supports the following: QFN (Quad Flat Pack No-Lead) components. Molded Components - Capacitor, Inductor and Diode. MELF components - diodes and resistors. Precision wire wound inductors. SOT 89 packages. Dual
Page: Altium Designer DXP library list
Libraries supplied with DXP (2002 Release) Summary of libraries: 46 manufacturers 854 manufacturer device libraries (+4 miscellaneous) 72 PCB footprint libraries Actel Actel 3200DX FPGA.IntLib Actel A40MX FPGA.IntLib Actel A42MX FPGA.IntLib Actel A54SX FP
Page: Altium Designer Environment Preferences
Altium Designer の環境プリファレンス http://videos.altium.com/trainingcenter/player.html?ep=1156 Altium Designer streamlines the setting of environment options across all document editors and servers, by centralizing these options within a single, context-sensitive
Page: Altium Designer Home Page
Altium Designer Home Page Altium Designer Home ページ The Home page within Altium Designer provides a 'central hub' from which to access many common tasks and support resources. The page is designed to present relevant information in a clear, concise and pow
Page: Altium Designer Licensing System
Japanese System licencjonowania Altium Designer Retrieving and Configuring Your Altium Designer Software License Altium Designer provides a streamlined licensing system, enabling you to get licensed and up-and-running with your Altium Designer Software in
Page: Altium Designer Panels
Main article: Working with Panels Workspace panels are an essential part of the Altium Designer environment. Editor-specific panels provide an alternate view into the data being edited, while system-wide panels, like the Projects panel, give access to des
Page: Altium Designer RTL Reference
The Altium Designer Run Time Library (RTL) is composed of several Application Programming Interfaces (APIs) that are associated with specific document kinds and design object types. The System API deals with low level objects and routines used by Altium D
Page: Altium Designer Summer 08 - Downloads
Downloads There are now three ways to update Altium Designer. 1. Web updates from within Altium Designer Altium Designer includes the ability to check for, download or automatically install updates from within the Altium Designer software. This is configu
Page: Altium Designer Summer 08 - Local Update Server Setup
Altium Designer has the ability to check Altium’s server for available software updates. Altium Designer Summer 08 - Software Updates Alternatively, updates can be downloaded and stored on an internal file server. Altium Designer can then be configured to
Page: Altium Designer Summer 08 - Release Info
Altium Designer Summer 08 The Summer 08 release of Altium Designer lets you create your next-generation of electronic products. Embedded designers, board-level experts and system engineers have access to over 150 new power packed features and enhancements
Page: Altium Designer Summer 08 - Software Updates
Software updates for Altium Designer Summer 08. Self-contained updates These updates can only be applied to a Summer 08 installation of Altium Designer. The following downloads include a setup program that is used to install the update. Service Pack 1 Bui
Page: Altium Designer Summer 09 - Downloads
Downloads There are three ways to update Altium Designer. 1. Web updates from within Altium Designer Altium Designer includes the ability to check for, download or automatically install updates from within the Altium Designer software. This is configured
Page: Altium Designer Summer 09 - Local Update Server Setup
Altium Designer has the ability to check Altium’s server for available software updates. Information on other ways of updating Altium Designer Alternatively, updates can be downloaded and stored on an internal file server. Altium Designer can then be conf
Page: Altium Designer Summer 09 - Release Information
Altium Designer Summer 09 The summer 09 release of Altium Designer is now available and introduces new design technologies and concepts to help electronics designers innovate, exploit advances in technology, and make the task of designing a product and ge
Page: Altium Designer Summer 09 - Software Updates
Software updates for Altium Designer Summer 09 Self-contained updates These updates can only be applied to a Summer 09 installation of Altium Designer. The following downloads include a setup program that is used to install the update. Service Pack 1 Buil
Page: Altium Designer Summer 09 Libraries
Altium Designer board-level design integrated libraries   The below library downloads are deemed to be 'frozen libraries'. The content of these ZIPs was built at the time of the launch of Altium Designer Summer 9, and will not be updated. Updated versions
Page: Altium Designer Summer 09 library list
Libraries supplied with Altium Designer Summer 09 Summary of libraries: 114 manufacturers/brands 1,039 manufacturer device libraries (+3 miscellaneous) 95,315 Components for Board Design 406 PCB footprint libraries 18 system-level design libraries for FPG
Page: Altium Designer Version Numbering
Altium Designer のバージョン表示   From Altium Designer 2013 onward, a simple version scheme is employed to visually indicate the version of Altium Designer currently installed and being used. This scheme reflects the main version of the software, as well as the
Page: Altium Designer Viewer
Altium Designer Viewer The Altium Designer Viewer (henceforth also referred to as the Viewer) provides you with the ability to view, print, cross probe and explore design projects and documents that have been created using Altium Designer. As a true viewe
Page: Altium Designer Viewer - Environment
Altium Designer Viewer supports the display of multiple design documents of differing type. Schematic, PCB, OpenBus, CAM and OutJob documents are opened and viewed within their respective Document Editors. All other text-based document types (e.g. embedde
Page: Altium Designer Viewer - Generating Output
Altium Designer Viewer allows you to open, view, and generate output from, Output Job Configuration files (*.OutJob). Such files – also referred to as Output Job files – typically contain a host of manufacturing and design information. These files are ope
Page: Altium Designer Viewer - Home Page
The Home page within Altium Designer Viewer provides a 'central hub' from which to access many common tasks and support resources. The page is designed to present relevant information in a clear, concise and powerful way – giving you streamlined access to
Page: Altium Designer Viewer - Viewing PCB Documents
In Altium Designer Viewer PCB documents are opened in the PCB Editor. The tools and utilities needed to inspect the PCB design and generate reports and assembly drawings, are available in the editor. When the PCB Editor is active (i.e. a PCB document (*.P
Page: Altium Designer Viewer - Viewing Schematic Documents
In Altium Designer Viewer schematic documents are opened in the The Schematic Editor, which allows you to check and print the schematic sheets that make up a design project. The tools and utilities needed to perform checks for electrical and drafting viol
Page: Altium Designer What's New - Previous Releases
Altium Designer の新機能 - 以前のバージョン(S09 以前) New Features in the Summer 09 Release of Altium Designer The Summer 09 release of Altium Designer continues the process of keeping you plugged into a continuous stream of new features and technologies. They are desi
Page: Altium Designer Winter 09 - Downloads
Downloads There are now three ways to update Altium Designer. 1. Web updates from within Altium Designer Altium Designer includes the ability to check for, download or automatically install updates from within the Altium Designer software. This is configu
Page: Altium Designer Winter 09 - Local Update Server Setup
Altium Designer has the ability to check Altium’s server for available software updates. Altium Designer Winter 09 - Software Updates Alternatively, updates can be downloaded and stored on an internal file server. Altium Designer can then be configured to
Page: Altium Designer Winter 09 - Release Information
Altium Designer Winter 09 The Winter 09 release of Altium Designer brings significant new and enhanced features to unify the design process, helping you create a real return on your innovation. It's the next phase in our commitment to update our solution
Page: Altium Designer Winter 09 - Software Updates
Software updates for Altium Designer Winter 09. Self-contained updates These updates can only be applied to a Winter 09 installation of Altium Designer. The following downloads include a setup program that is used to install the update. Service Pack 1 Bui
Page: Altium DXP (2002 release) Libraries
Altium Designer board-level design integrated libraries The below library downloads are deemed to be 'frozen libraries'. The content of these ZIPs was built at the time of the launch of Altium DXP (2002), and will not be updated. Updated versions of many
Page: Altium Freeware End-User License Agreement
Altium Freeware End-User License Agreement IMPORTANT - READ CAREFULLY This Altium Freeware End-User License Agreement ("EULA") is a legal agreement between you (either an individual person or a single legal entity, who will be referred to in this EULA as
Page: Altium Hardware
Japanese Altium Hardware Altium has developed a reconfigurable hardware development system called the Desktop NanoBoard NB2DSK01. This system can be reconfigured and extended with plug-in daughter board and peripheral board cards. Daughter boards provide
Page: Altium Hardware - FAQs
Browse the following areas for answers to various questions that are asked when developing device intelligence using Altium hardware. NanoBoards Daughter Boards Peripheral Boards Other Hardware
Page: Altium Hardware FAQs - Daughter Boards
Use the following links to browse through the frequently asked questions relevant to development using one of Altium's daughter boards. Can I build my own daughter board? Daughter boards may be constructed, provided the pinout requirements of the motherbo
Page: Altium Hardware FAQs - NanoBoards
Use the following links to browse through the frequently asked questions relevant to development with one of Altium's NanoBoards. Can I use the daughter boards I have for my NanoBoard-NB1 with the Desktop NanoBoard NB2DSK01? All of the daughter boards ava
Page: Altium Hardware FAQs - Other Hardware
Page: Altium Hardware FAQs - Peripheral Boards
Use the following links to browse through the frequently asked questions relevant to development using one or more of Altium's peripheral boards. Can I build my own peripheral board? Peripheral boards may be constructed with any required resources, provid
Page: Altium Instrument Dashboard
仮想測定器のダッシュボード FPGA Field Instrumentation FPGA-based soft instruments – "Virtual Instruments" – are a powerful way of embedding debug tools inside FPGAs. With Altium Designer's Custom Instrument component, fully customizable instrumentation can be created
Page: Altium Instrument Dashboard - How Instruments are Displayed
When creating and configuring a custom instrument in Altium Designer, options are available relating to display of the instrument when accessed using the Altium Instrument Dashboard. These options allow the instrument to be displayed either in a standard
Page: Altium Instrument Dashboard - How it Works
Similar to Altium Designer's Devices view, the Altium Instrument Dashboard is enabled by ensuring its Live option is enabled – right-click on the system tray icon for the Dashboard to access the menu containing this and other commands. Once live, it essen
Page: Altium Instrument Dashboard - Supported Instruments
The Altium Instrument Dashboard has primarily been built to access embedded Custom Instruments, but the following virtual instruments are also supported: Frequency Generator (CLKGEN) Frequency Counter (FRQCNT2) Terminal Console (TERMINAL) Legacy Digital I
Page: Altium Legacy - P-CAD Legacy Program
Altium Legacy - P-CAD Legacy Program (CN) Altium Legacy - P-CAD Legacy Program (DE) Altium Legacy - P-CAD Legacy Program Altium Legacy - P-CAD Legacy Program (FR) Altium Legacy - P-CAD Legacy Program (JP) Altium has formally ceased development of our P-CA
Page: Altium Legacy - What Happened To Protel?
Altium Legacy - What Happened To Protel? (CN) Altium Legacy - What Happened To Protel? (DE) Altium Legacy - What Happened To Protel? Altium Legacy - What Happened To Protel? (FR) Altium Legacy - What Happened To Protel? (JP) Altium has a long history of i
Page: Altium Legacy Customer Program
Altium Legacy Customer Program (CN) Altium Legacy Customer Program (DE) Altium Legacy Customer Program Altium Legacy Customer Program (FR) Altium Legacy Customer Program (JP) Still using a retired Altium software product such as Protel or P-CAD and thinki
Page: Altium Library Development Center
The Altium Library Development Center (ALDC) provides an extensive suite of libraries to accompany Altium products. Libraries are created using specifications obtained from manufacturers and various industry standards and then made available to users with
Page: Altium People
Dr Marty Hauff Ben Jordan
Page: Altium Vault Server - Administration Improvements
Altium Vault Server - 管理機能の改善   The latest release of the Altium Vault Server brings several improvements to administration of the vault through its browser-based interface. These improvements are available, irrespective of whether access is made through
Page: Altium Vault Server - Centralized Supply Chain Management
Altium Vault Server - 集中化されたサプライチェーン管理   Each Altium Vault Server instance has its own dedicated Part Catalog. This is a managed local part catalog database, dedicated to the management and tracking of manufacturer parts and their associated supplier part
Page: Altium Vault Server - Visual Indication of Current User
Altium Vault Server - 現在のユーザを表示   When signing-in to an Altium Vault Server through an external web browser, indication of who is signed in is presented, in terms of the user's full name. Visual indication of signed-in user when accessing an Altium Vault
Page: Altium Vault Server - Visual Indication of Licensing Status
Altium Vault Server - ライセンスの状態を表示   Access to an Altium Vault Server requires a license. And since the Altium Vault Server is a service or application ('app') plugged into the DXP Apps Server platform, a license is also required to connect to that platfor
Page: Altium Vault Technology
Altium Vault テクノロジー Altium Vaults Feature Comparison Altium's Vault technology provides the foundation for Altium's Design Data Management solution. A distinct design solution in its own right, an Altium Vault works in harmony with Altium Designer to prov
Page: Altium Vaults - Information for IT Departments
While installation and use of Altium Vault Technology – in the form of an Altium Vault Server or Altium Personal Vault – is detailed across other pages within the Wiki, the aim of this page is to provide a single, detailed resource for an organization's I
Page: AltiumDesigner2013((Home Page))
AltiumDesigner2013((Home ページ))   The Home page has been totally redesigned in Altium Designer 13.0, presenting a number of distinct views and sub-views with which to browse and manage various aspects of the software. This includes views for License Manage
Page: AltiumLive
AltiumLive AltiumLive Content Store Forums BugCrunch Dashboard FAQs Introduction to the AltiumLive Dashboard Altium Designer Altium Hardware Altium Instrument Dashboard Altium Designer Viewer The work involved in getting a product from concept to manufact
Page: AltiumLive - BugCrunch
AltiumLive - BugCrunch AltiumLive - BugCrunch From an early age we have, for the most part, been raised to both fear and loathe bugs. When we see a bug crawling across the floor, we feel both curious and repelled – should we inspect and play with it, or z
Page: AltiumLive - Content Store
AltiumLive - Content Store AltiumLive - Content Store Introducing the AltiumLive Content Store. The Content Store is an area in AltiumLive dedicated to content - content that is invaluable for helping the designer learn about and work in Altium Designer.
Page: AltiumLive - Dashboard
AltiumLive - Dashboard AltiumLive - Dashboard   FAQs Glossary When we purchase something, we like to (quite rightly) take ownership of, and control how, that something is used. Having established an account with Altium, you will typically have purchased t
Page: AltiumLive - FAQs
AltiumLive - FAQ   Parent article: AltiumLive General Wall Content Store Forums BugCrunch Blog Dashboard Software AltiumLive Content Store Forums BugCrunch Dashboard Introduction to the AltiumLive Dashboard Use the following links to browse through freque
Page: AltiumLive - Forums
AltiumLive - フォーラム Detailed information on the AltiumLive Forums will appear at some stage here in the future. Stay tuned and 'watch this space' as they say. The AltiumLive Forums are the channels for Altium customers – and interested observers – from all
Page: AltiumLive - Ideas
We all have opinions on how we think the software should behave or the feature set it should offer. Perhaps you've got a suggestion on how an existing feature in the software could be enhanced or improved. Or new functionality that you think would be a co
Page: AltiumLive - Wall
Keeping abreast of the things that interest us is a natural part of everyday life. Fanning the pages of that physical (or virtual) newspaper, for example, is a daily ritual that most of us indulge in, to stay knowledgeable on current affairs. That's not t
Page: AltiumLive Dashboard - FAQs
AltiumLive Dashboard - FAQ General Company Profile Users Groups Licenses AltiumLive - Dashboard Managing Users Managing Groups Managing Licenses Use the following links to browse through frequently asked questions relevant to the AltiumLive Dashboard. For
Page: AltiumLive Dashboard - Glossary
AltiumLive Dashboard - słownik AltiumLive Dashboard - 用語集 Account The Account is each Organization's record of details in Altium's database. Account details that can be accessed via the AltiumLive Dashboard include: Profile - including Company details suc
Page: AltiumLive Dashboard - Managing Groups
AltiumLive Dashboard - zarządzanie grupami AltiumLive Dashboard - グループ管理 Managing Users Managing Licenses Parent article: AltiumLive - Dashboard Main page for managing groups within the Dashboard. The Groups page is part of the AlitumLive Dashboard. Use t
Page: AltiumLive Dashboard - Managing Licenses
AltiumLive Dashboard - zarządzanie licencjami AltiumLive Dashboard - ライセンス管理 Managing Users Managing Groups Parent article: AltiumLive - Dashboard Main page for managing licenses within the Dashboard. The Licenses page is part of the AltiumLive Dashboard.
Page: AltiumLive Dashboard - Managing Users
AltiumLive Dashboard - zarządzanie użytkownikami AltiumLive Dashboard - ユーザ管理 Managing Groups Managing Licenses Parent article: AltiumLive - Dashboard Main page for managing users within the Dashboard. The Users page is part of the AltiumLive Dashboard. U
Page: An Insiders Guide to the Query Language
This document attempts to de-mystify what queries are, how and why they are used, and to provide insights into how these queries can be executed. An appendix includes useful query examples. Queries can be used to filter specific objects in Schematic Libra
Page: An Introduction to Altium Vaults
The introduction of the Altium Vault is a key part of Altium’s overall Design Data Management solution, and plays a pivotal role in Altium's evolving Vault-Driven Electronics Design methodology. As a centralized repository of refined design data, the Vaul
Page: An Overview of Electronic Product Development in Altium Designer
As every engineer knows, developing an electronics product is a highly detailed and multi-stepped process. From the idea on the back of the envelope through to the working board ready to drop into its housing, there are many tasks to complete and many opp
Page: Analyzing Bus Signals in an OpenBus System
Being able to interrogate bus signals between two devices in a system can be very handy from a debugging perspective. In the schematic world, this is done simply by 'tapping off' the signals you want to look at and feeding them to the appropriate instrume
Page: Analyzing Design Nets
As part of its LiveDesign methodology, Altium Designer provides you with the ability to analyze nets in an FPGA design, while it is running on the target physical device. Where a design net is connected directly to a pin of the physical device, you have t
Page: Angular Dimension
Baseline Dimension Center Dimension Datum Dimension Leader Dimension Linear Dimension Linear Diameter Dimension Radial Dimension Radial Diameter Dimension Standard Dimension Description An angular dimension is a group design object. It allows for the dime
Page: Arc
Description An arc is a primitive design object. It is essentially a circular track segment that can be placed on any layer. Arcs can have a variety of uses in PCB layout. For example, they can be used when defining component outlines on the overlay layer
Page: Arc Support for Multi-Route Tools (AD10)
Japanese Enhanced Routing Capabilities Altium Designer 10 sees the Multi-Trace and Differential Pair interactive routers enhanced to now support arc cornering styles. Use the Shift+Spacebar shortcut to change the corner style as required between: Track 45
Page: Assembling the NanoBoard 3000
Before you can use your NanoBoard 3000, you will need to perform the following steps:   Clean the plastic surfaces (A) with the wipe provided.     Peel off the self-adhesive non-slip feet (B) from the back sheet and fix them in place on each of the side p
Page: Assembly Outputs
How do I generate manufacturing files The Assembly Outputs category of the OutputJob Editor allows you to create the following Output Generators: Assembly Drawings Generates pick and place files Configuring Assembly Drawing Output Generators Depending on
Page: Assembly Testing (PCB)
Related article: Fabrication Testing Assembly testing relates to the testing of a printed circuit board at the post-assembly phase of manufacture, after the board has been populated with all components specified in its associated Bill of Materials (BOM).
Page: Assigning Design Nets to Physical Pins of the FPGA Device
Any net that you wish to connect to a physical pin of the target device must be wired to a port on the top schematic sheet for the FPGA design project. Upon compilation of the design, the top sheet is scanned and all nets that connect to ports are assumed
Page: Assigning Nets to FPGA Pins in the Constraint File
The net (or port)-to-physical pin assignments also need to be defined in a constraint file. You can manually define the assignments, or let the place and route tools assign them and then import the assignments back into the constraint file. Typically ther
Page: Attaching a Daughter Board to the Desktop NanoBoard
A daughter board is mounted onto the NB2DSK01 motherboard by plugging its 100-way Male connectors into the motherboard's 100-way Female connectors – designated HDR_T1, HDR_L1 and HDR_B1. These are referred to as 'NANOCONNECT' interfaces. Figure 1. Daughte
Page: Attaching a Peripheral Board to a NanoBoard
Main article: Peripheral Boards A peripheral board is mounted onto the NanoBoard by plugging its 100-way Male docking connector into the motherboard's corresponding 100-way Female docking connector (referred to as a 'NANOCONNECT' interface). The board can
Page: Attaching the Debugger to a Running Application
Japanese 挂接调试器到运行中的应用程序 CPU Debug Attach Debugging an embedded application currently requires pausing the processor as you enter a dedicated debug session. The application stops running and you are effectively having to 'start from the beginning' of the c
Page: Attaching the NB2DSK-SPK01 to the Desktop NanoBoard
The NB2DSK-SPK01 is mounted onto the NB2DSK01 motherboard by plugging its 16-way Male connector into the motherboard's corresponding 16-way Female connector, which is located on the solder-side of the motherboard. Figure 1. Speaker board connector on the
Page: Auto trax
Altium Freeware End-User License Agreement IMPORTANT - READ CAREFULLY This Altium Freeware End-User License Agreement ("EULA") is a legal agreement between you (either an individual person or a single legal entity, who will be referred to in this EULA as
Page: Auto-Loading Fabrication Output into the CAM Editor
When generating Gerber, ODB++, NC Drill or IPC-356-D output, you can specify that one or more of these types of output be automatically imported into a new CAM Editor document (.cam). This is performed using the Output Job Options dialog (Figure 1), acces
Page: Automatic Firmware Update Wizard
Kreator automatycznego uaktualniania firmware'u Main article: NanoBoard 3000 - Firmware Updates The Automatic Firmware Update wizard. The Automatic Firmware Update wizard is used to perform all changes to the operating firmware (Primary boot image) curren
Page: Automatic FPGA-PCB Linking - Choosing the FPGA Configuration
The second page of the FPGA To PCB Project Wizard allows you to choose the configuration that will be used for targeting the FPGA design to the PCB. The configuration uses one or more constraint files to define the FPGA device to be used and its associate
Page: Automatic FPGA-PCB Linking - Choosing the Target PCB Project
After choosing the FPGA configuration, the actual target PCB project must now be defined. This is performed on the third page of the FPGA To PCB Project Wizard. By default, the Wizard will generate a new project (PCB Project1.PrjPCB), with the project fil
Page: Automatic FPGA-PCB Linking - Configuring the FPGA Component Schematic Sheet
Whether the PCB project already exists or is being newly created, the relationship between the FPGA project and its corresponding component in the PCB project has to be managed in some way. This is achieved using a dedicated, auto-generated schematic shee
Page: Automatic FPGA-PCB Linking - Configuring the Sheet Symbol Schematic Sheet
As part of the PCB project, you have the option of defining the 'owner' of the FPGA Component sheet (holding the component symbol for the FPGA device). The final page of the FPGA To PCB Project Wizard allows you to define the owner as a sheet symbol which
Page: Automatic FPGA-PCB Linking - Verifying that the Projects are Linked
Verification that the automatic linking of the projects has been successful can be made from two places: By interrogating the Sub-Design Links region of the Component Properties dialog, for the FPGA component on the PCB project's schematic sheet. When suc
Page: Automatic Route to Mouse Modes
Japanese Related articles: PCB Routing, Interactively Routing a Net This feature delivers the following two additional interactive modes: Autoroute to the current cursor location on the current layer. Autoroute to the current cursor location across differ
Page: Automatically Linking FPGA and PCB Projects
Perhaps the easiest and more streamlined method of linking an FPGA project to a PCB project, is to create the PCB project directly from within the FPGA design, with the aid of the FPGA To PCB Project Wizard. This method automatically links the two project

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Page: Baseline Dimension
Angular Dimension Center Dimension Datum Dimension Leader Dimension Linear Dimension Linear Diameter Dimension Radial Dimension Radial Diameter Dimension Standard Dimension Description A baseline dimension is a group design object. It allows for the dimen
Page: Batch Download of Items from a Vault
Vault から Item をバッチでダウンロード   Altium Designer 13.2 brings the ability to select multiple Items in an Altium Vault, and have the source entities for those Items downloaded, en masse, into a newly created, and linked, single source library, or folder, as appl
Page: Batch Update of Parameters from a Library Component
Varying a component and/or its additional parameters for an assembly variant is not always an easy task. The change could be trivial, requiring a different value for a capacitor and no other changes. It could also be near impossible - having to remember a
Page: Ben Jordan
Ben Jordan obtained BEng in Computer Systems Engineering (First Class Honours) by distance through the University of Southern QLD (who now have a marvellous lab of Altium Nanoboard-IIs). Ben commenced employment with Altium Ltd. in Frenchs Forest, NSW, on
Page: Beta Updates
Altium Designer 6.0.2.5494 Beta List of Updates PCB The .Legend String now expands correctly in PCB Prints. PLOT_FILE_NAME & .PRINTOUT_NAME Strings now expands correctly in in Gerber & ODB++ outputs when TrueType fonts are used. Altium Designer 6.0.2.5479
Page: Blanket Directives in Schematic Documents
回路図ドキュメントの Blanket Directive   The Blanket Directive is a powerful feature in Altium Designer's Schematic Editing domain. It enables other parameter-set based directives to quickly be applied to a group of nets, simply by 'covering' those nets with a blan
Page: Board Implementation
Board Implementation Getting Started with PCB Design Preparing the Board for Design Transfer Design Rules Editors, Panels and Object Reference Internal Power and Split Planes Polygon Pours and Copper Regions PCB Routing Pin, Differential Pair and Sub-Part
Page: Board Implementation - FAQs
Page: Board Insight Panel
Function The Board Insight panel provides you with plenty of useful information about any objects currently under the cursor. Once open, this panel keeps you informed if you briefly pause the cursor over PCB objects in the design editor window, with no ke
Page: Board Shape
Description The board shape, also referred to as the board outline, is a closed polygon that defines the boundary, or extents, of the PCB. The board shape is used to determine the extents of the power planes when calculating plane edge pull back, used whe
Page: Bootstrapping the Daughter Board FPGA on the NanoBoard-NB1
The NanoBoard-NB1 provides the ability to bootstrap the FPGA device located on the currently inserted daughter board, at power-up. An 8MBit Flash memory device(M25P80) is used to store the programming file required for implementing the design within the F
Page: Bringing the Chains Together - the NanoTalk Controller
The NanoBoard includes Altium's proprietary communications protocol, referred to as NanoTalk. This protocol defines and provides a communication path between a PC running Altium Designer and one or more NanoBoards. NanoTalk is implemented as part of the f
Page: Browser-based Management of an Altium Vault Server
Altium Vault Server のブラウザベースの管理   Parent article: Altium Vault Technology For an Altium Vault Server only, connection is also possible through its browser-based interface, providing the URL to that vault is known. The browser interface allows for administ
Page: Browsing Structure Classes in a PCB
Parent article: Class Structure in the PCB Set the <b>PCB</b> panel's mode to <tt>Structure Classes</tt> to browse the overall class hierarchy for the PCB document. The display in the main design window<br>will change to reflect the filtering applied as y
Page: BT656 - Accessible Internal Registers
The following sections detail the internal registers for the BT656 Controller that can be accessed from the host processor. Mode Register (MODE) Address: 0h Access: Read and Write Value after Reset: 0000_0014h This register is used to set the operational
Page: BT656 - Block Diagram
Figure 1 shows a high-level block diagram for the BT656 component. Figure 1. BT656 Controller block diagram. For information on the internal registers for the BT656 that can be accessed from the host processor, see Accessible Internal Registers.
Page: BT656 - Color Conversion
The color space used for the digital video data is YCbCr (4:2:2 sampling). As part of the reformatting of the BT.656 stream into the simple memory image, this color space must be converted into RGB or Grey-scale. When the active video data from the stream
Page: BT656 - Controller State Machines
The BT656 Controller has two Finite State Machines, the tasks of which can be summarized as follows: Input Stream FSM – this FSM involves a number of states, with its purpose essentially divided into two tasks. In the first task, it waits for an EAV code,
Page: BT656 - Host to Controller Communications
Communications between a 32-bit host processor and the BT656 Controller are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessib
Page: BT656 - Interrupts
Two interrupt lines are sent from the BT656 Controller to the host processor on the INT_O[1..0] bus. Bit 0 of this bus is used for the Frame Interrupt, used to notify the processor that a new frame is being written to the external memory. The frame interr
Page: BT656 - Operational Overview
After an external reset, you will need to initialize the BT656 Controller. This involves: Writing the value for the start address in external memory to the Controller's START register. Writing the value for the size of the external memory space to be used
Page: BT656 - Pin Description
The following pin description is for the BT656 component when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals wil
Page: BT656 - Transmitted Pixel Data
The value that is sent to the FIFO is constructed using the value in the RGB or GREY register, in accordance with the color mode defined in the MODE register (MODE4..2). The value is stored in an intermediate register – FIFO_IN. Table 1 summarizes the pix
Page: BT656 - Wishbone Video Capture Controller
Figure 1. BT656 Wishbone Video Capture Controller. There are many video decoder ICs on the market that take S-Video or Composite video signals as input, and convert these signals to the ITU-R BT.656 format. One example is the TVP5150A from Texas Instrumen
Page: Building an Integrated Library
統合ライブラリの作成   Integrated libraries combine schematic libraries with their related PCB footprints and/or SPICE and signal integrity models, all together in a non-editable form. All model information is copied into the integrated library from the model libra
Page: Building Script Projects
This tutorial covers the general aspects of the Scripting System and the use of Borland Delphi Objects and DXP Object Models in scripts. Netlister, Board Outline Copier and Query Expression scripts are developed using the DXP Object Models to illustrate t
Page: Bus-based System Design
Japanese FPGA Design for Embedded Developers A 'bus-based system' is the term used to describe a method of connecting functional 'building blocks' of logic into an overall system, using generic buses. In this way, you can quickly assemble a system that in

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Page: C++ Support in Altium Designer
C++ Support  As software development technology has progressed there has been a distinct trend towards higher-level, more abstract software development languages and tools – from machine code, to assembly language, to procedural languages to object orient
Page: Cadstar Importer
Cadstar インポーター The CADSTAR importer has been added to the Altium Designer Winter 09 release to assist users translating CADSTAR design and library files to Altium Designer format. Supported Version and File Format The importer supports CADSTAR version 9 o
Page: CAM Editor
CAM Editor Introduction CAM Editor Feature Highlights CAM Editor Apertures CAM Editor Panels for Fabrication and Assembly CAM Editor Reverse Engineering PCBs CAM Editor Data Verification CAM Editor Imports and Exports
Page: CAM Editor Apertures
This article looks at the apertures, aperture lists and aperture tables as they are used in Altium Designer's CAM Editor (CAMtastic®). PCB layers are created from photographic film which has been exposed to light. Apertures are the physical openings throu
Page: CAM Editor Data Verification
This tutorial follows the steps that must be taken in order to extract a valid netlist from imported Gerber, NC Drill or ODB++ files, run a design rule check (DRC) on that data in Altium Designer's CAM Editor (CAMtastic®) and verify or modify the data. Al
Page: CAM Editor Feature Highlights
This article looks at some of the feature highlights of Altium Designer's CAM Editor (CAMtastic®), including ODB++ import and export, advanced panelization and direct export to Altium Designer's PCB Editor. One of the essential steps in the development an
Page: CAM Editor Imports and Exports
This tutorial looks at importing and exporting a variety of CAM files using Altium Designer's CAM Editor (CAMtastic®). During this tutorial, we will investigate the Quick Load command by importing supplied Gerber and ODB++ files into the CAM Editor. Quick
Page: CAM Editor Introduction
This article introduces Altium Designer's CAM Editor (CAMtastic) and describes basic editing modes and the CAM Editor workspace panels. Altium Designer's CAM Editor offers a variety of tools, the most basic of which are for viewing and editing CAM data. O
Page: CAM Editor Panel
Function The CAM panel provides quick access to the list of layers that are available in the current CAM document and also enables you to view design-related information arising from commands including object querying, netlist extraction and Design Rule C
Page: CAM Editor Panels for Fabrication and Assembly
This article describes the CAM Editor (CAMtastic®) tools for panelization and NC routing commands. Traditionally, design engineers have used CAM tools for verification only, visually reviewing their Gerber and Drill outputs before forwarding these files t
Page: CAM Editor Reverse Engineering PCBs
This article looks at reverse-engineering a PCB layout directly from CAM files loaded into Altium Designer's CAM Editor (CAMtastic®). After importing CAM data into a CAM document, you will notice that the Export to PCB option is grayed-out, regardless of
Page: CANB_W - Accessible Internal Registers (Detailed)
The following sections detail the internal CAN registers that can be accessed from the host processor. Mode Register (MOD) Address in CAN memory – 00h Register value after hardware reset – 00000001 Register value after software reset or when in Bus-Off st
Page: CANB_W - Accessible Internal Registers (Summary)
The following table lists all of the internal CAN registers. Table 1. Internal CAN registers - summary listing. <table class='confluenceTable'><tbody> <tr> <th class='confluenceTh'> <DIV align="center">Location in CAN address space</DIV> </th> <th class='
Page: CANB_W - Architectural Overview
The following sections detail the architectural elements that comprise the CANB_W Controller. FIFO Control Unit (FifoCtrl) with Receiver FIFO (RAM) The Receive FIFO stores received and accepted messages from the CAN-bus. The Receive Buffer register repres
Page: CANB_W - Block Diagram
Figure 1 shows a high-level block diagram for the CANB_W component. Figure 1. CANB_W block diagram. For information on the key architectural components within the Controller, see Architectural Overview. For information on the internal registers for the CA
Page: CANB_W - Dataflow Diagrams
Figure 1 below describes the dataflow between the two main Finite State Machines in the Receiver and Transmitter blocks. Figure 1. Main dataflow between Receiver and Transmitter. Figures 2 and 3 illustrate state machine diagrams for the Receiver and Trans
Page: CANB_W - Pin Description
The pinout of the CAN Controller has not been fixed to any specific device I/O, thereby allowing flexibility with user application. The CAN Controller contains only unidirectional pins – inputs or outputs. The following pin description is for the CANB_W w
Page: CANB_W - Wishbone CAN Controller with Direct Addressing
Figure 1. CANB_W - Wishbone CAN Controller with Direct Addressing. The CAN Controller component (CANB_W) is a stand-alone, Wishbone-compliant controller, for a Controller Area Network conforming to the CAN 2.0B specification. It provides an interface betw
Page: Catering for Memory-Based Peripherals
A design might feature one or more processors and a range of memory-based peripheral devices, all of which require access to the same physical memory. Figure 1 shows an example of using an Arbiter component to share access to a single physical memory devi
Page: Center Dimension
Angular Dimension Baseline Dimension Datum Dimension Leader Dimension Linear Dimension Linear Diameter Dimension Radial Dimension Radial Diameter Dimension Standard Dimension Description A center dimension is a group design object. It allows for the cente
Page: Chaining Multiple Desktop NanoBoards
Each Desktop NanoBoard NB2DSK01 contains NanoTalk Master and Slave connectors that allow multiple NanoBoards to be daisy-chained together. The Hard and Soft JTAG chains are passed between boards using a 10-way IDC cable – from the Slave connector on the f
Page: Chaining Multiple NanoBoards
Each NanoBoard contains NanoTalk Master and Slave connectors that allow multiple NanoBoards to be daisy-chained together. The Hard and Soft JTAG chains are passed between boards using a 10-way IDC cable – from the Slave connector on the first board to the
Page: Choosing Functions to Implement in Hardware
Although functions that are destined for implementation in hardware can be 'identified' directly at the source code level, Altium Designer provides a more friendly, straightforward and intuitive interface, as part of the configuration of its ASP periphera
Page: Choosing the Variant in an Output Job File
Japanese Output Job Editor Enhancements Project Configurations and Releases Related article: Design to Manufacturing Altium Designer allows you to drive the outputs of your PCB project using the base (non-varied) design, or by nominating the use of a defi
Page: Circuit Simulation
回路シミュレーション Working with the Sim Data Editor Support for PSpice Models in Altium Designer SPICE Model Creation from User Data Creating and Linking a Digital SimCode Model Linking a Simulation Model to a Schematic Component Using SIMetrix SIMPLIS Circuit Si
Page: Class Structure in the PCB
http://wiki.altium.com/pages/viewpage.action?pageId=25071640 PCB のクラス構造 Structured Classes in the PCB Editor Altium Designer already provided high-quality, robust support for generation of classes (Component and Net) when transferring the design from the
Page: Clearance Constraint
Clearance 制約   Description Defines the minimum clearance allowed between any two primitive objects on a copper layer. Use this rule to ensure that routing clearances are maintained. Constraints Minimum Clearance   the value for the minimum clearance requi
Page: Clearance Rule Sub-Scopes for Differential Pairs
Japanese Altium Designer includes Sub-Scopes as part of its clearance rule checking in the PCB Editor, specifically aimed at addressing the issue of clearances pertaining to Differential pairs. Previously, a board containing n Differential pairs would req
Page: Client Processes
This section covers the Client (System) processes and their parameters (if any). The Client module is the backbone of Altium Designer. ArrangeAllWindows process Description The ArrangeAllWindows process can arrange opened windows (documents) in Altium Des
Page: Clipboard Panel
Function The Clipboard panel can store and display a number of objects that can be added (pasted) to various document types within Altium Designer at any stage, allowing for multiple copy/paste operations. The panel supports a variety of data formats, dep
Page: CLKGEN - Pin Description
Table 1. CLKGEN Pin description. <DIV align="center">Name</DIV> <DIV align="center">Type</DIV> <DIV align="center">Polarity/ Bus size</DIV> <DIV align="center">Description</DIV> TIMEBASE <DIV align="center">I</DIV> <DIV align="center">Rise</DIV> External
Page: Cloud Preferences
Japanese Cloud Preference Storage Altium Designer provides the ability to access your settings through the cloud. Wherever you design, at home, in the office or at a different site, you can work in your preferred environment using the cloud preferences. I
Page: CmpLib Editor Enhancements
CmpLib エディタの改善   Vault-based components are released into an Altium Vault from a Component Library, also referred to as a CmpLib (the file extension used for Vault Component Libraries). Components are defined in the CmpLib in a spreadsheet-like way, one c
Page: CmpLib Generation from Active Database Library
データベース ライブラリから CmpLib 生成   Component Management Vault-Based Components Component Libraries and Component Definitions Component Release Manager Vault-Driven Electronics Design When migrating from an older component management methodology – that uses databa
Page: CmpLib Generation from Active Schematic Library
回路図ライブラリから CmpLib 生成   Component Management Vault-Based Components Component Libraries and Component Definitions Component Release Manager Vault-Driven Electronics Design When migrating from an older component management methodology – that uses simple mod
Page: Collaborate, Compare and Merge Panel
Parent article: Collaborative PCB Design The <b>Collaborate, Compare and Merge</b> panel. The Collaborate, Compare and Merge panel is command-central for performing a copper comparison between two versions of the same PCB design. It requires that the boar
Page: Collaborative PCB Design
Japanese PCB Layout Collaboration As the saying goes, many hands make light work. One of the long-held dreams of board designers is to be able to have multiple people working on the same board, at the same time. While this task might not seem overly compl
Page: Combinatorial vs. Multi-Cycle Circuits
The C-to-Hardware Compiler can generate two types of circuit from the C source code for an exported function – Combinatorial and Multi-cycle. Referred to as the 'interface mode' for the C Code Symbol, the type of circuit is specified as part of the C Code
Page: Common ESD Prevention Techniques
With all boards/devices susceptible to ESD, it is important to follow standard antistatic handling procedures. As the ESD generally involved with a NanoBoard will be the result of contact with the human body, the following are often considered when creati
Page: Compile Errors Panel
Compile Errors パネル   Function The Compile Errors panel is used to display detailed information about the offending object(s) associated with a Compiler-specific message being cross-probed from the Messages panel. You can use the panel to jump to the objec
Page: Compiled Object Debugger Panel
Compiled Object Debugger パネル   Function The Compiled Object Debugger panel enables you to view detailed information about an object or document selected in the Navigator panel, or to interrogate an offending object selected in the Compile Errors panel. Co
Page: Component
Description A component footprint is a group design object that represents a physical device on a PCB. A footprint may include such items as pads for connecting to the pins of a device, a physical outline of the package and device mounting features. Avail
Page: Component Clearance
This rule specifies the minimum distance that components can be placed from each other. Component clearance includes clearance between 3D models used to define component bodies (both STEP and extruded (simple) types) and even non-component free-floating m
Page: Component Libraries and Component Definitions
コンポーネントライブラリとコンポーネント定義 create a new vault-based component? batch-create multiple vault-based components? update the models within managed components? Related article: Vault-Based Components On the design side, each design component released to an Altium V
Page: Component Management
コンポーネント管理   Next Generation Component Management Next Generation Component Management Parent article: Vault-Driven Electronics Design Related articles: Vault-Based Components, Part Catalog and Part Choices One of the fundamental principles to Altium's Des
Page: Component Orientations
Description Specifies allowable component orientations. Multiple orientations are permitted, allowing the Autoplacer to use any of the enabled orientations. Constraints Allowed Orientations the chosen orientations that are made available for use by the Cl
Page: Component Parameters in Smart PDF Output
スマート PDF でのコンポーネント パラメータ   Component Parameters in PDF Adding additional 'smarts' to its Smart PDF feature, Altium Designer now includes component parameters in generated PDF output. Generate your PDFs in the manner to which you have become accustomed, ei
Page: Component Reference
This reference outlines the supported components for scripting and their main properties and methods. This reference outlines the graphical components for scripting including their properties and methods. These components accessed from the Tool Palette pa
Page: Component Release Manager
コンポーネントリリースマネージャ   batch-create multiple vault-based components? Related articles: Vault-Based Components, Vault-Based Domain Models, Component Libraries and Component Definitions The Component Release Manager provides a centralized release 'console' with
Page: Component, Model and Library Concepts
コンポーネント、モデル、ライブラリの概要   This article explains Altium Designer components, models and libraries, and their relationships. Approaches for identifying and managing component-to-library relationships are explored, as well as the search sequence for locating mo
Page: Configurable Generic Library
Altium Designer Winter 09 heralds the arrival of a new integrated library of configurable generic FPGA logic components – FPGA Configurable Generic.IntLib. The aim of this library is to provide many of the logic components found in the existing FPGA Gener
Page: Configuring a 32-bit Processor
The architecture of a 32-bit processor can be configured after placement on the OpenBus System document, or schematic sheet, using the Configure (32-bit Processors) dialog, an example of which is shown in Figure 1. Access to this dialog depends on the doc
Page: Configuring a Custom Instrument
Configuration of a Custom Instrument component is performed using the Custom Instrument Configuration dialog (Figure 1). Access this dialog by right-clicking over the component and choosing the Configure command from the menu that appears. Figure 1. Confi
Page: Configuring Output Media (Output Job File)
To configure Print, PDF or File Generation Settings, right-click on your Output Medium and choose from either PDF Setup , Generated Files Setup or Printer Setup depending on your selection. You can also configure Printer Setup and Page Setup for output ge
Page: Configuring Pin Swapping for an FPGA Component
Before any pin swapping can occur, swap-ability information must first be set up for the FPGA component in question. Pin swap settings are stored in the schematic component's pins, while the option to allow pin swapping on a specific component is enabled
Page: Configuring the Arbiter Component
Configuration of an Arbiter component is performed using the Configure OpenBus Arbiter dialog (Figure 1). Access this dialog by right-clicking over the component and choosing the Configure command from the menu that appears. Alternatively, double-click on
Page: Configuring the Constraints
Configurations provide a way for an Altium Designer project to be managed parametrically. For embedded projects this could allow a separate set of settings to be maintained for a debug version and a release version of the product. For a PCB project config
Page: Configuring the Crosspoint Switch Module
The Crosspoint Switch module can be configured after placement on the schematic sheet using the Crosspoint Switch Configuration dialog (Figure 1). To access this dialog, simply right-click over the symbol for the device and choose the Configure command fr
Page: Configuring the Digital IO Module
The Digital I/O Module can be configured after placement on the schematic sheet using the Digital I/O Configuration dialog (Figure 1). To access this dialog, simply right-click over the symbol for the device and choose the Configure command from the conte
Page: Configuring the Interconnect Component
Configuration of an Interconnect component is performed using the Configure OpenBus Interconnect dialog (Figure 1). Access this dialog by right-clicking over the component and choosing the Configure command from the menu that appears. Alternatively, doubl
Page: Configuring the Logic Analyzer
The LAX instrument can be configured after placement on the schematic sheet. Simply right-click over the schematic symbol for the instrument and choose the Configure command from the bottom of the pop-up menu that appears (e.g. Configure U2 (LAX) for a lo
Page: Configuring the OpenBus System
The key purpose of the OpenBus System feature is to facilitate creation of a processor-based system as quickly, as intuitively and, perhaps more importantly, as painlessly as possible. Building the actual system is a breeze, but what about configuration?
Page: Configuring the Private License Server on Windows 7, Windows Vista, Windows Server 2003 and above
Main article: Using a Private Server License The security model for Microsoft Windows 7, Windows Vista, Windows 2003 Server and Windows 2008 Server operating systems does not allow the icon for a Windows Service to be displayed while you are remote connec
Page: Connected FPGA Scripts
Altium Designer already offers a Custom instrument, with the ability to design and script a simple virtual instrument in an FPGA. The Summer 09 release improves and extends these abilities by allowing more powerful script applications to be built in a mor
Page: Connecting Multiple Memory Devices
The nature of your FPGA design may warrant the use of several memory devices, possibly of differing type, each of which requires to be mapped into a specific location within the processor's address space. Within the OpenBus System, this can be readily ach
Page: Connecting Multiple Peripheral IO Devices
Typically in an FPGA design, the processor will need to interface to multiple peripheral I/O devices, many of which are interfacing controllers for communicating with external devices or circuitry. Each of these peripherals may contain any number of inter
Page: Connecting Production PCBs to the Desktop NanoBoard NB2DSK01
As well as chaining multiple Desktop NanoBoards together, you can also attach your own board to the NB2DSK01, through a JTAG connection, for inclusion into the system. Up to two user boards can be connected to each NanoBoard in the system. This enables yo
Page: Connecting Single Slave Devices
Although a single memory or peripheral I/O device can be connected directly to the respective MEM or IO port of the processor, use of an Interconnect component simplifies matters. Without an Interconnect component, there are a few limitations to note and
Page: Connecting Slave Devices to a 32-bit Processor
Physical memory is connected to the processor's External Memory interface. Peripheral devices are connected to the processor's Peripheral I/O interface. The following linked pages explore the methods of connection, from a single slave device, through to a
Page: Connecting the Altium USB Adapter to a NanoBoard-NB1
Altium's USB JTAG Adapter enables you to create a JTAG link (incorporating multiplexed Hard and Soft JTAG chains) from your PC (running Altium Designer) to a NanoBoard-NB1, using a USB connection. On the PC side, connect the USB JTAG Adapter to a spare US
Page: Connecting the Altium USB Adapter to a Xilinx LiveDesign Evaluation Kit
Altium's USB JTAG Adapter enables you to create a JTAG link (incorporating multiplexed Hard and Soft JTAG chains) from your PC (running Altium Designer) to a LiveDesign Evaluation Kit, using a USB connection. On the PC side, connect the USB JTAG Adapter t
Page: Connecting the Altium USB Adapter to an Altera LiveDesign Evaluation Kit
Altium's USB JTAG Adapter enables you to create a JTAG link (incorporating multiplexed Hard and Soft JTAG chains) from your PC (running Altium Designer) to a LiveDesign Evaluation Kit, using a USB connection. On the PC side, connect the USB JTAG Adapter t
Page: Connecting the NanoBoard 3000
Before you can communicate with (and download a design to) the NanoBoard 3000, the board needs to first be prepared. This involves connecting it to your PC and supplying power to the system. To set up the NanoBoard 3000, complete the following steps: Ensu
Page: Connecting the NanoBoard NB2
Before you can communicate with (and download a design to) the NanoBoard NB2 (NB2DSK01), the board needs to first be prepared. This involves connecting it to your PC, installing your daughter board and supplying power to the system. To set up the NanoBoar
Page: Connecting User-Developed Boards
As well as chaining multiple NanoBoards together, you can also attach your own board to the NanoBoard for inclusion into the system. Up to two user boards can be connected to each NanoBoard in the system. This enables you to extend Altium's LiveDesign met
Page: Connecting with Altium
Japanese Related article: Disconnecting from Altium's On-Demand Services Altium Designer includes a growing number of on-demand style features, made available to you upon signing in to your Altium Account through the secure Altium portal. Such features in
Page: Connection
Description Connection lines are the visual representation of the logical connectivity between net objects. Each of these lines, connecting one pin in a net to another pin in the net, is called a From To . The entire set of connections (From Tos) for a de
Page: Connectivity and Multi-Sheet Design
Japanese The structural and connective considerations involved in multi-sheet design are discussed, then the different browsing tools that let you verify net connectivity across source documents are described. Engineers turn to multi-sheet design for vari
Page: Constraint File Reference
FPGA designs are captured in the Altium Designer design environment as schematic/OpenBus System/HDL documents. Implementation information, such as device pin allocations and pin electrical properties are not stored in these source files, they are stored i
Page: Constraint Files - Base Constraint Elements
The following sections detail the base constraint elements (non-FPGA-specific) that can be included in a constraint group. Record Summary  – Defines purpose of entry in the constraint file. Values       – FileHeader, Constraint TargetKind Summary  – Defin
Page: Constraint Files - Constraint Basics
Each line in a constraint file is referred to as a constraint group, since it applies one or more constraint requirements to an entity in the design. The following examples show a variety of different constraint groups. Example 1 Record=Constraint | Targe
Page: Constraint Files - Defining Constraints
Constraints are normally defined in constraint files, using the constraint editor. To add a new constraint file to a project right-click on the project name, then from the Add New to Project submenu select Constraint File . Constraints can be defined by t
Page: Constraint Files - FPGA-specific Constraint Elements
The following is a list of FPGA-specific constraint definitions. These constraints must be used in conjunction with the device vendor's component specifications, to ensure that a particular constraint is supported in that device. FPGA_CLOCK FPGA_CLOCK_DUT
Page: Constraint Files - Importing Vendor-generated Pin Constraints
Any pins (ports) that were not assigned in the constraint file prior to place and route are automatically assigned a physical pin during place and route. These assignments are needed before the FPGA design can be linked to the PCB design. To import the pi
Page: Content and Use of the Output Job Editor
Japanese The OutputJob Editor becomes active when the active document is an *.OutJob file. Create a new file of this type for the active project by either: Using the File » New » Output Job File command Right-clicking on the project name in the Projects p
Page: Controlling Access to Content in an Altium Vault Server
Altium Vault Server 内の Content へアクセスするためのコントロール   An Altium Vault Server provides secure handling of data with high integrity, while providing both Design Team and Supply Chain access to that data as needed. This latter aspect, of who can access a vault,
Page: Controlling the Color of Connection Lines
コネクションラインの色をコントロール   The connection lines that join the various nodes in each net are invaluable during the routing process, to help guide you as you route across and through the board. When the design is initially transferred all connection lines are giv
Page: Converting Parts to Ports
If you have used port plug-in components in your design – to represent resources on the NanoBoard, daughter board or peripheral boards – you will probably prefer to display them as ports when the design is moved to your own board. Altium Designer provides
Page: Coordinate
Description A coordinate is a group design object. It is used to mark the X (horizontal) and Y (vertical) distance of a point in the design workspace with respect to the current origin. Coordinates can be placed on any layer. Availability Coordinates are
Page: Copyright
Altium Designer® Help Materials Open Content License Altium Ltd. ("Altium") provides technical information concerning its Altium Designer® product (the "Help Materials") in an online, open content format. The Help Materials provided herein are available i
Page: CoreMP7 Data Organization
Data organization refers to the ordering of the data during transfers. There are two general types of ordering: BIG ENDIAN – the most significant portion of an operand is stored at the lower address LITTLE ENDIAN – the most significant portion of an opera
Page: CoreMP7 Interrupts
The Altium Designer CoreMP7 component supports both hardware exceptions (interrupts) and software exceptions. In terms of hardware exceptions, only the Interrupt Request exception (IRQ) is supported. The Fast Interrupt Request exception (FIQ) is not and t
Page: CoreMP7 Memory Space
The CoreMP7 uses 32-bit address buses providing a 4GByte linear address space. All memory access is in 32-bit words, which creates a physical address bus of 30-bits. Memory space is broken into three main areas, as illustrated in Figure 1. Figure 1. Memor
Page: CoreMP7 Pin Description
The pinout of the CoreMP7 has not been fixed to any specific device I/O – allowing flexibility with user application. The CoreMP7 contains only unidirectional pins (inputs or outputs).   The following pin description is for the processor when used on the
Page: Counter Module
How do I use the Frequency Counter instrument? Figure 1. Counter module. The Counter module (FRQCNT2) provides a two-channel, three-mode frequency counter. For each input signal, the device counts the number of edges – rising or falling – detected within
Page: Create Pad From Track Script
Create Pad From Track Script Maybe not so useful, but please try it. Download Version 0.6 CreatePadFromTrack_v06.zip Notes Launch this script, then click on any track in PCB editor. Pad is placed at same size and location on current layer. Track is not de
Page: Creating a Configuration
Constraints can be divided over a number of constraint files, and a project can include a number of different constraint files that are used to target the design to different implementations. To allow you to group constraint files and to move easily from
Page: Creating a Constraint File and Specifying the Device
To add a new constraint file to your project, right-click on the project name in the Projects panel, and select Add New to Project » Constraint File from the menu that appears.   The new constraint file will open as the active document. To specify the tar
Page: Creating a Custom Pad Shape
Tworzenie padów o niestandardowych kształtach Japanese Standard Pad Attributes Altium Designer's standard pad object can: Be set to a number of different shapes, including round, rectangular, rounded rectangular and octagonal. Be sized differently in the
Page: Creating a Multi-channel Design
This tutorial shows how to create a multi-channel design in the Schematic Editor, including the use of sub-sheets, sheet symbols and the Repeat keyword. Setting room and designator formats and viewing the channel designator assignments are also covered. A
Page: Creating a Soft Design License
Japanese Related article: Licensing and the NanoBoard Each Altium NanoBoard is shipped with a 12-month Soft Design license of Altium Designer. The license in each case is linked to that particular NanoBoard. To access and use the license, it first needs t
Page: Creating a Stub FPGA Project
A Stub FPGA project can be created in one of two ways: By running the PCB To FPGA Project Wizard As a result of changing signal characteristics within the PCB project The following sections take a closer look at the creation of the Stub FPGA project in th
Page: Creating and Linking a Digital SimCode Model
Due to the complexity of digital devices it is generally not practical to simulate them using standard, non-event-driven SPICE instructions. For this reason Altium Designer's Mixed-Signal Circuit Simulator includes a special descriptive language that allo
Page: Creating Design Rules
デザインルールの作成   Parent article: Design Rules Management of the design rules for the current board design, is performed from the PCB Rules and Constraints Editor dialog (Design » Rules). The following sections take a look at working with this dialog to browse
Page: Creating Library Components
ライブラリコンポーネントの作成     The tutorial was created for releases prior to Altium Designer 10. Path information, Footprints, Models may not be included with Altium Designer 10. It is possible to Download Examples and Reference Designs and to Download Libraries fr
Page: Creating Output Media
Once output generators have been added and configured, you can create one or many types of output media including Print, Publish to PDF and File Generation which can each include a number of output generators. The availability of output generators for sel
Page: Crosspoint Switch Module
Figure 1. Example Crosspoint Switch module. The Crosspoint Switch module (CROSSPOINT_SWITCH) facilitates signal switching within an FPGA design. It allows you to specify any number of input and output blocks, all of which share a common signal block struc
Page: CROSSPOINT_SWITCH - Pin Description
The Crosspoint Switch Module is very simple in its pinout. It can have any number of input blocks and any number of output blocks. The block structure, which is the same for all input and output blocks, can contain any number of signals. A signal can be a
Page: custom
Page: Custom Instrument
Figure 1. Example Custom Instrument. The Custom Instrument component (CUSTOM_INSTRUMENT) is a fully-customizable 'virtual' instrument with which to monitor and control signals within an FPGA design. As part of the instrument's configuration you are able t
Page: Custom Instrument - Code Tab
The Code tab of the Custom Instrument Configuration dialog is where you write the underlying event handling code – procedures and/or functions that are called into action when corresponding trigger events, relating to the components and controls on the in
Page: Custom Instrument - Design Tab
The Design tab of the Custom Instrument Configuration dialog is where you design the look and feel of the instrument's panel – the customized GUI that you access to interact with the instrument at run-time. Initially, you will be presented with a 'shell'
Page: Custom Instrument - Signals Tab
This tab of the Custom Instrument Configuration dialog is divided into the following five regions. Instrument Options This region of the tab allows you to define some basic options for the Custom Instrument: Title – this is the caption used at the bottom-
Page: Custom Instrument Code - Hooking the Script up to the Instrument
Writing script event handling procedures and functions is literally 'half the battle'. You could have the most elegant and functionally smart code there is, and it will still remain dormant unless it is correctly linked, or hooked-up, to the relevant comp
Page: Custom Instrument Code - Manipulating Signal IO through a Script
Input and output signals can be linked directly to the controls placed on the customized GUI for the instrument. For many cases, this direct use of the signals will be sufficient. However, to fully harness the power of the Custom Instrument and give you f
Page: Custom Instrument Code - Writing Code in a Syntax-Aware Text Editor
The Code tab of the Custom Instrument Configuration dialog supports basic syntax highlighting. Should you wish to write your script within the comfort of a code-aware editor within Altium Designer, simply click the Open in Code Editor button at the bottom
Page: Custom Instrument Enhancements
Custom Instruments have been enhanced in the Winter 09 release of Altium Designer, mainly in support of the standalone Altium Instrument Dashboard – new for the Winter 09 release. When configuring a Custom Instrument, you will find new options available o
Page: Custom Instrument GUI - Available Instrument Controls
Table 1 lists all of the instrument controls available for use when designing the GUI for a Custom Instrument. These controls are specifically for use with the Custom Instrument. Table 1. Instrument controls available for use on the instrument form. <DIV
Page: Custom Instrument GUI - Available Standard Components
Table 1 lists all of the standard components available for use when designing the GUI for a Custom Instrument. These are components that are used as standard in scripting and, as such, can all be found on the Tool Palette panel that is used when writing g
Page: Custom Instrument GUI - Directly Hooking up Signal IO to a Control
In Manipulating Signal IO through a Script, we will look at how IO signals wired to a Custom Instrument can be manipulated to a greater degree by use of scripting. However, use of a script is not a prerequisite for use of the instrument. Indeed, the contr
Page: Custom Instrument GUI - Editing Placed Objects on the Form
After an object has been placed on the form, there are a variety of ways in which its location, size, or appearance can be edited. These methods of editing generally fall into two categories – graphical editing, directly within the form, and editing perfo
Page: Custom Instrument GUI - Placing Objects onto the Form
To place a component or control on the form, simply click on the relevant icon on the Palette panel and then click at the desired location within the bounds of the form. Alternatively, double-click on an icon to have the object placed centrally on the for
Page: Custom Instrument Tutorial - Accessing the Instrument Panel
Now the design has been programmed into the physical FPGA device, we can finally access the customized GUI we created for the instrument in real-time. This is the exciting final part of our tutorial – the part where we get to 'play' with the fruits of our
Page: Custom Instrument Tutorial - Capturing the Design
Let's go ahead and capture our simple custom instrument design in an FPGA project within Altium Designer. Create a new FPGA project and save it with the name Custom_Instrument_Design.PrjFpg, in a new folder called Custom Instrument Tutorial. Add a new sch
Page: Custom Instrument Tutorial - Configuring the Custom Instrument
Configuration of the Custom Instrument component is carried out from within the Custom Instrument Configuration dialog (Figure 1). We briefly visited this dialog when capturing the design, in order to define the instrument's interface IO signals. <FONT si
Page: Custom Instrument Tutorial - Defining Base Options for the Instrument
From the design schematic, right-click on the symbol for the Custom Instrument and choose Configure from the context menu. The Custom Instrument Configuration dialog appears, with the Signals tab active by default (Figure 1). <FONT size="1"><I>Figure 1. S
Page: Custom Instrument Tutorial - Designing the Custom GUI
Now it's time to create the GUI – the customized panel for the instrument that will be accessed once the design is programmed into the daughter board FPGA. Click on the Design tab at the bottom of the Custom Instrument Configuration dialog. You will be pr
Page: Custom Instrument Tutorial - Hooking the Script up to the GUI
We have our designed instrument panel. We have our DelphiScript code to achieve the desired manipulation of the output. We now need to hook our script up to the GUI, so that the relevant procedure can be called when a certain event occurs within the panel
Page: Custom Instrument Tutorial - Processing the Design
Now that the design has been fully captured and targeted to our daughter board FPGA device, we can go ahead and process the design – ultimately creating the required FPGA programming file with which to program the target device. Ensure that your Desktop N
Page: Custom Instrument Tutorial - Targeting the Design to the FPGA Device
Now we are finished with the capture phase of our design, we need to specify which physical FPGA device we want to use – the target for our design and the end medium into which the design will ultimately be programmed and run. For this tutorial, we will t
Page: Custom Instrument Tutorial - Writing the Script
Before we look at the script itself, let's recap what we want to have happen, in relation to the data output from our custom instrument: In normal operation, the output should be placed under the control of the Numeric Panel control. If either the 'DAUGHT
Page: Custom Logic
How do I use VHDL or Verilog in an FPGA design? How do I create and share an FPGA Core? Quite literally, custom logic is logic (or intelligence) that you create yourself and add in to your design. You would typically add your own custom logic into a desig
Page: Custom Logic Tutorial - Adding the C-based Custom Logic
Now we have our 'shell' design, we need to add-in the custom logic – the functional heart of the design, written in C code. The ability to incorporate underlying C code into an FPGA design is an extension to the concept of design hierarchy. Similar to the
Page: Custom Logic Tutorial - Capturing the Design
Let's go ahead and capture our simple accumulator design in an FPGA project within Altium Designer. First, create a new FPGA project and save it with the name CHC_Accumulator.PrjFpg, in a new folder called C Custom Logic Tutorial. Add a new schematic docu
Page: Custom Logic Tutorial - Configuring the Custom Instrument
We need to configure the Custom Instrument component. Rather than do this from scratch however (which is outside the focus of this tutorial), we will use one of the key benefits of the instrument – the fact that its configuration information is stored in
Page: Custom Logic Tutorial - Creating the C Code Symbols
Now we have our C source files, we can create corresponding C Code Symbols for each, directly from them. Open the design schematic (CHC_Accumulator.SchDoc).   From the main menus, choose Design » Create Code Symbol From C File. In the Choose Document to P
Page: Custom Logic Tutorial - Processing the Design
Now that the design has been fully captured and targeted to our daughter board FPGA device, we can go ahead and process the design – ultimately creating the required FPGA programming file with which to program the target device. Ensure that your Desktop N
Page: Custom Logic Tutorial - Targeting the Design to the FPGA Device
Now we are finished with the capture phase of our design, we need to specify which physical FPGA device we want to use – the target for our design and the end medium into which the design will ultimately be programmed and run. For this tutorial, we will t
Page: Custom Logic Tutorial - Using the Accumulator
Now the design has been programmed into the physical FPGA device, we can 'play' with our simple accumulator design and test that it works! In the Devices view, double-click on the icon for the Custom Instrument, located in the Soft Devices chain. The asso
Page: Custom Logic Tutorial - Wiring the Design
With our C-coded custom logic hooked into the design, all that's left is to wire up the design. Go ahead and wire up the design as shown in Figure 1.   Figure 1. Final design - fully wired.   Save the schematic and project documents.   Compile the project
Page: Custom Logic Tutorial - Writing the Code
Our design requires two custom logic circuits: A clock pulse circuit – which takes as input a control signal from the Custom Instrument component. The circuit needs to generate a 1 clock cycle pulse (High) when this input control signal goes High. An accu
Page: Customization of Net Colors
PCB Highlighting  The Summer 09 release brings even greater control over the highlighting of nets on your PCB documents, using your own overriding color scheme. Now, instead of purely having a net object colored using its respective layer color, you can a
Page: Customizing Output Media
Setting the Order of Outputs You can set the order in which your outputs appear within each Output Medium. As you enable your outputs, they are numbered consecutively. If you remove one of the outputs from your Output Medium, the numbers are re-ordered ac
Page: Customizing the Altium Designer Resources
Altium Designer リソースのカスタマイズ   Resources in an editor are the menu bars, toolbars and the shortcut key tables. All the commands available from the menus are also available for adding to or deleting from these resources. Customization overview Behind each r

D

Page: Daisy Chain Stub Length
Description Specifies the maximum permissible stub length for a net with a daisy chain topology. Constraints Maximum Stub Length the value for the maximum stub length allowed. (Default = 1000mil). Rule Classification Unary How Duplicate Rule Contentions a
Page: Database Library Migration Tools
Database Library 移行ツール   This document provides detailed information on the migration tools associated with Altium Designer's Database Library features (DBLib and SVNDBLib). Direct support for OrCAD CIS is also covered. Altium Designer provides the abilit
Page: Datum Dimension
Angular Dimension Baseline Dimension Center Dimension Leader Dimension Linear Dimension Linear Diameter Dimension Radial Dimension Radial Diameter Dimension Standard Dimension Description A datum dimension is a group design object. It allows for the dimen
Page: Daughter Board Common Services
In addition to the user-available IO, the daughter board connectors on the NB2DSK01 motherboard provide pins for a series of other functions, including implementation of the NanoTalk communications protocol, power, and programming of the FPGA device. The
Page: Daughter Board Common-Bus Flash Memory
The daughter board includes Flash memory as part of the common-bus block of memory resources available to the FPGA. The Flash memory is provided in the form of an S29GL256N11FFIV10 device (from Spansion). The Page Mode 256Mbit device is manufactured using
Page: Daughter Board Common-Bus SDRAM
The daughter board includes Synchronous Dynamic RAM as part of the common-bus block of memory resources available to the FPGA. The SDRAM is provided in the form of two MT48LC16M16A2TG devices (from Micron Technology). Each device is a 256Mbit, high-speed
Page: Daughter Board Common-Bus SRAM
The daughter board includes Static RAM as part of the common-bus block of memory resources available to the FPGA. The SRAM is provided in the form of two 4Mbit, high-speed CMOS SRAM devices. Each device is organized as 256K x 16 bits – combined together t
Page: Daughter Board Docking Connectors
A 3-connector daughter board has three 100-way Male connectors. These are used to connect the daughter board to the NB2DSK01 motherboard, which has corresponding 100-way Female connectors ('NANOCONNECT' interfaces). Figure 1. Example docking connectors on
Page: Daughter Board ID Memory
Board identification is handled courtesy of a DS2406 device (from Dallas Semiconductor). Although the device is actually a dual-addressable switch, it is used for the additional 1kbit of memory that it possesses. Figure 1. 1-Wire memory used to<br>contain
Page: Daughter Board Independent SRAM
The daughter board includes independent Static RAM as part of the memory resources available to the FPGA device, or more specifically the design running within. The term 'independent' is used in this case to distinguish this SRAM – which is interfaced usi
Page: Daughter Board Power (Including 1.2V and 2.5V)
In addition to the 3.3V and 5V supply voltages and ground signals fed to the daughter board from the NB2DSK01 motherboard, the daughter board also has its own 1.2V and 2.5V supplies. The 1.2V supply is generated by passing the regulated 5V supply through
Page: Daughter Board Power (Including 1.2V only)
In addition to the 3.3V and 5V supply voltages and ground signals supplied to the daughter board from the NB2DSK01 motherboard, the daughter board also has its own 1.2V supply. This supply is generated by passing the regulated 5V supply through a low-volt
Page: Daughter Board Power and Program LEDs
The daughter board provides the following two LEDs: Power LED – this will light (RED) when the daughter board is correctly plugged into the motherboard and the NB2DSK01's power is switched on. It signifies presence of the 3.3V supply to the board. Program
Page: Daughter Boards
Japanese Altium's NanoBoard architecture is unique in that target programmable devices are housed on separate satellite boards, referred to as daughter boards. These boards plug-in to the NanoBoard. By keeping each programmable device on its own daughter
Page: DB30 Xilinx Spartan-3 Daughter Board
Altium's Xilinx® Spartan™-3 daughter board DB30 provides an XC3S1500-4FG676C device, as well as a range of on-board memories available for use by a design running within that device. The DB30 has the following features: Xilinx Spartan-3 FPGA (XC3S1500-4FG
Page: DB31 Altera Cyclone II Daughter Board
Altium's Altera® Cyclone® II daughter board DB31 provides an EP2C35F672C8 device, as well as a range of on-board memories available for use by a design running within that device. The DB31 has the following features: Altera Cyclone II FPGA (EP2C35F672C8)
Page: DB32 LatticeECP Daughter Board
Altium's LatticeECP™ daughter board DB32 provides an LFECP33E-3FN672C device, as well as a range of on-board memories available for use by a design running within that device. The DB32 has the following features: LatticeECP FPGA (LFECP33E-3FN672C) On-boar
Page: DB36 Xilinx Virtex-4 LX Daughter Board
Altium's Xilinx® Virtex®-4 daughter board DB36 provides an XC4VLX25-10FF668C device, as well as a range of on-board memories available for use by a design running within that device. The DB36 has the following features: Xilinx Virtex-4 FPGA (XC4VLX25-10FF
Page: DB40 Altera Cyclone III Daughter Board
Altium's Altera® Cyclone® III daughter board DB40 provides an EP3C40F780C8N device, as well as a range of on-board memories available for use by a design running within that device. The DB40 has the following features: Altera Cyclone III FPGA (EP3C40F780C
Page: DB41 Xilinx Spartan-3AN Daughter Board
Altium's Xilinx® Spartan™-3AN daughter board DB41 provides an XC3S1400AN-4FGG676C device, as well as a range of on-board memories available for use by a design running within that device. The DB41 has the following features: Xilinx Spartan-3AN FPGA (XC3S1
Page: DB42 Xilinx Spartan-3A DSP Daughter Board
Altium's Xilinx® Spartan™-3A DSP daughter board DB42 provides an XC3SD1800A-4FGG676C device, as well as a range of on-board memories available for use by a design running within that device. The DB42 has the following features: Xilinx Spartan-3A DSP FPGA
Page: DB46 Xilinx Virtex-4 SX Daughter Board
Altium's Xilinx® Virtex®-4 daughter board DB46 provides an XC4VSX35-10FFG668C device, as well as a range of on-board memories available for use by a design running within that device. The DB46 has the following features: Xilinx Virtex-4 FPGA (XC4VSX35-10F
Page: Default Rules Created with a New PCB Document
The following design rules are created by default with a new PCB document. Except for specific Fanout Control rules, all default rules have a scope (Full Query) of All, meaning they apply to the whole board. For default rule constraints, refer to the indi
Page: Define Output Filenames using Expressions
Expression を使用して出力ファイル名を定義   A critical phase of the development cycle is releasing the documentation that is to be used for the fabrication and assembly of the PCB. In many companies it is common practice to use a standard naming scheme for all design do
Page: Defining & running Circuit Simulation analyses
回路シミュレーション解析の設定と実行   This tutorial starts by creating a simulation-ready schematic on which we will run our circuit simulation analyses. We will create a new project file first and then add a new blank schematic sheet. Creating a New Project To start the
Page: Defining a Configuration
A configuration is essentially just a named list of constraint files. Configurations belong to the project, and are stored in the project file. Configurations are created and managed in the Configuration Manager dialog, accessible through the Project menu
Page: Defining Assembly Variants
The controls for adding, defining and removing assembly variants for a design can be found in the Assembly Variant Management dialog (Figure 1), accessed by choosing Assembly Variants from the Project menu. Figure 1. Command Central - the Assembly Variant
Page: Defining Net Classes by Area on a Schematic
Blankets in Schematic  Altium Designer already allows you to create user-defined net classes on the schematic side using Net Class directives attached to each 'member' wire, bus or harness. When a PCB is created from the schematic source documents, the in
Page: Defining the Memory Map for a 32-bit Processor
An area that can be difficult to manage in an embedded software development project is the mapping of memory and peripherals into the processor's address space. The memory map, as it is often called, is essentially the bridge between the hardware and soft
Page: Defining Validation Reports in an Output Job File
Japanese Altium Designer provides the ability to define and run validation reports as part of an Output Job file. You can setup and run a Differences Report (using the comparator to determine if the source and PCB design documents are correctly in-sync),
Page: Delphi Script Reference
This section describes the DelphiScript language used by the Scripting Engine in Altium Designer and includes the following topics: Exploring the DelphiScript Language DelphiScript Source files Writing DelphiScript Scripts Differences between DelphiScript
Page: DelphiScript Keyword Reference
This reference covers the DelphiScript keywords used for the Scripting System in Altium Designer. The scripting system supports the DelphiScript language which is very similar to Borland Delphi (TM) 's Object Pascal language. The key difference is that De
Page: Deploying improved proxy support
Japanese Following are instructions on how to deploy the improved proxy support (delivered in Update 15, build 10.818.23272) in the Altium Installer and Altium Download Manager. Before you start The new Altium Designer Installer and Download Manager will
Page: Design Content Management
デザイン Content の管理   Parent article: Vault-Driven Electronics Design Related article: Managed Schematic Sheets The term 'Design Reuse' has become something of a cliché in the marketing of engineering products, perhaps primarily driven by how little of this
Page: Design Data Management System - FAQs
設計データ管理システム - FAQ General Design Repositories Altium Vault Vaults Panel Items and Item Revisions Vault-Based Components Part Choices Managed Schematic Sheets PCB Project Configurations Validation Board Design Release Process Lifecycle Management Publishin
Page: Design Insight
Design projects have quickly become complicated, involving a large number of varied design documents each with potentially massive amounts of data. Faster, easier and more intuitive project navigation available with Design Insight. Design Insight provides
Page: Design Portability, Configurations and Constraints
The design for an FPGA is captured in a set of schematic and/or HDL source files. As well as the symbols, wiring and HDL source that makes up the design, there is other essential information that must be captured. This can be broadly labeled as implementa
Page: Design Release Management
Design Release Management Design Release Management Demo Video Managing the process of releasing a design for prototype or production is a key aspect of the product development process and an important part of the overall enterprise data management functi
Page: Design Release Management Demo Video
Page: Design Repositories
Japanese Parent article: Vault-Driven Electronics Design A Design Repository is a centralized repository in which all design projects are stored. Owned by the design team, the Design Repository contains a high-resolution view of the history of the design
Page: Design Rule Checking
Chinese Japanese Design Rule Checking (DRC) is a powerful automated feature that checks both the logical and physical integrity of your design. Checks are made against any or all enabled design rules and can be made online, as you work, and/or as a batch
Page: Design Rules
Chinese Japanese PCB design is no longer a matter of placing tracks to create connections. High speed logic combined with smaller and more complex packaging technologies place new demands on the PCB Designer. It is not possible to satisfy all the requirem
Page: Design Synthesis
Synthesis is the process of translating the schematic and behavioural VHDL descriptions of the design into a low-level form suitable for the vendor place and route tools. The synthesis engine first creates an intermediate VHDL description of the design, a
Page: Design to Manufacturing
Japanese How do I generate manufacturing files Completing the Schematic Design and PCB layout is only the first part of the process that culminates in the fabrication and assembly of your PCB. The link between your design and the finished board are the Sc
Page: Design Verification
デザインの確認 Verifying Your Design in Altium Designer Circuit Simulation Signal Integrity Analysis Project Compiler Error Reference
Page: Design Workspace
Design workspace You can open and edit multiple design projects in Altium Designer. Provision is also made for you to be able to save any set of open projects as a Design Workspace (*.DsnWrk). This can prove to be a highly efficient option when working wi
Page: Designing Custom FPGA Logic using C
Altium Designer provides the ability to add custom logic to an FPGA design, where that logic is 'captured' in an underlying C source file, and referenced using a C Code Symbol primitive. The latter is a type of sheet symbol that is essentially used to 'ex
Page: Desktop NanoBoard NB2DSK01
NanoBoard NB2 Desktop NanoBoard Technical Overview Altium's Desktop NanoBoard NB2DSK01 is a unique, reconfigurable hardware platform that harnesses the power of today's high-capacity, low-cost programmable devices to allow rapid and interactive implementa
Page: Desktop Stereo Speaker Assembly NB2DSK-SPK01
The Desktop Stereo Speaker Assembly NB2DSK-SPK01 is essentially a satellite speaker board, catering for enhanced audio output through provision of high-quality speakers. It is attached to the underside of Altium's Desktop NanoBoard NB2DSK01 and subsequent
Page: Detecting and Reporting Out of Date Items in the Item Manager
Item Manager で Out of Date Item を検出しレポート   During the course of product development, it is normal for changes to occur. For example, component models may be updated to a new drawing standard, or component definitions may have been updated to add new param
Page: Detecting Differences in your Design
The very heart of the synchronization feature is the Comparator, without which detection of differences that exist between design documents would not be possible. The Comparator can compare the component and connective information between almost all kinds
Page: Differences Panel
Differences パネル   Function The Differences panel is used to display all logical differences that have been found by the Comparator when comparing design documents (for example, comparing the source document hierarchy for a project against the PCB design d
Page: Differential Pair Routing
Differential Pair Routing Specifies the maximum, minimum distances between tracks in a differential pair routing and the maximum distance that the pair is allowably uncoupled (ie: less than minumum gap or more than maximum gap). Constraints Min Gap   the
Page: Digital IO Module
How do I use the Digital IO instrument? Figure 1. Example Digital I/O module. The configurable Digital I/O module (DIGITAL_IO) provides separated inputs and outputs, allowing you to monitor and display signal levels, as well as define control signals for
Page: Digital SimCode Reference
This comprehensive reference describes the Digital SimCode™ language - used to specify simulation models for digital devices. The reference includes in-depth descriptions for each of the constituent functions for the language.   Due to the complexity of d
Page: DIGITAL_IO - Pin Description
The DIGITAL_IO Module is very simple in its pinout. It can have any number of input signals and any number of output signals. A signal can be any number of bits wide, but this will typically be 8-, 16- or 32-bit for most designs. Each signal can also be c
Page: Dimensions
Angular Dimension Baseline Dimension Center Dimension Datum Dimension Leader Dimension Linear Dimension Linear Diameter Dimension Radial Dimension Radial Diameter Dimension Standard Dimension
Page: Disconnecting from Altium's On-Demand Services
Altium の On-Demand サービスから切断   Related article: Connecting with Altium Through the secure Altium portal, Altium Designer is able to present a range of productivity-enhancing, 'on-demand' services, including on-demand licensing and updated exchange rates wh
Page: Document Management - Auto save, Local History and External Version Control
Chinese Japanese Developing an electronic product in an environment like Altium Designer results in a large number of electronic files. These files are valuable, they are your company's IP (Intellectual Property), and must be stored and maintained in an a
Page: Document Options
Options specific to the active schematic document are defined in the Document Options dialog, which can be accessed by choosing Design » Document Options from the main menus. This dialog provides controls for defining the look and feel of the schematic sh
Page: Documentation and Help
資料とヘルプ   Altium Designer is a fully-featured design environment, capable of performing all aspects of the electronic product development process. That means there's a lot to learn! Support for learning is provided on a number of levels, including: F1 dyna
Page: Documentation Outputs
How do I generate manufacturing files The Documentation Outputs category of the OutputJob Editor allows you to create the following Output Generators: Composite Drawing Logic Analyzer Prints OpenBus Prints PCB 3D Prints PCB Prints Schematic Prints SimView
Page: Download Altium Libraries
The Altium Library Development Center (ALDC) provides an extensive suite of libraries to accompany Altium products. All PCB Libraries are developed under an ISO 9001 certified quality assured system. Libraries are available for Altium Designer, DXP (2002
Page: Download Examples and Reference Designs
Japanese Parent article: Installation and Content Management There's no better way to showcase the features and functionality available in Altium Designer, than by example. In addition to the large range of examples, a variety of full reference designs ar
Page: Download Information 2004
Download Info Downloading Zip Files Many of our download files are contained within Zip format compressed files. On some systems you may require a utility to extract the contents of the zip file. If a zip file appears to be empty when using the Open butto
Page: Download Information 6
Download Info Downloading Zip Files Many of our download files are contained within Zip format compressed files. On some systems you may require a utility to extract the contents of the zip file. If a zip file appears to be empty when using the Open butto
Page: Download Libraries
Japanese Parent article: Installation and Content Management With the release of Altium Designer 10, components are now delivered through the Altium Vault and accessed for placement during design-time via Altium Designer's Vault Explorer panel. Vault-base
Page: Download PDF Learning Guides
PDF ラーニングガイドのダウンロード   Parent article: Installation and Content Management The PDF Learning Guides are deemed to be 'frozen documentation'. Their content has not, nor will not, be updated. Documents that are still accurate today may become inaccurate in th
Page: Downloading a Test Project to the Desktop NanoBoard NB2DSK01
To ensure that Altium Designer and the Desktop NanoBoard NB2DSK01 are installed and functioning correctly, follow the steps below to compile and synthesize an example project, from within Altium Designer, and download it to the FPGA resident on the curren
Page: Downloading a Test Project to the NanoBoard 3000
中文 To ensure that Altium Designer and the NanoBoard 3000 are installed and functioning correctly, follow the steps below to process an example project, from within Altium Designer, and download it to the User FPGA resident on the NanoBoard. For this test
Page: Downloads & Updates for Altium Designer - Previous Releases
Use the following links to access pages relevant to downloads and updates for previous releases of Altium Designer. Altium Designer Summer 09 Altium Designer Winter 09 Altium Designer Summer 08 Altium Designer 6 Altium Designer 2004 To take advantage of t
Page: Downloads & Updates for Altium Designer 2004
Service Packs Service Pack 4 (Build Number 8.4.03.3664)is the latest release of Altium Designer. We recommend that you update your software to this latest version to have all the new features, enhancements and improvements. IMPORTANT NOTE: Service Pack 4
Page: Downloads & Updates for Altium Designer 6
Downloads There are now three ways to update Altium Designer. 1. Web updates from within Altium Designer Altium Designer 6 includes the ability to check for, download or automatically install updates from within the Altium Designer software. This is confi
Page: Downloads & Updates for Altium Designer Summer 08
Downloads There are now three ways to update Altium Designer. 1. Web updates from within Altium Designer Altium Designer includes the ability to check for, download or automatically install updates from within the Altium Designer software. This is configu
Page: Downloads & Updates for Altium Designer Summer 09
From the 1st November, 2013, changes have been made to the license management system that affect the way in which you login to the Altium Portal from within Altium Designer. This change affects customers using Standalone or Private Server Licenses of Alti
Page: Downloads & Updates for Altium Designer Winter 09
Altium Designer Winter 09 The Winter 09 release of Altium Designer brings significant new and enhanced features to unify the design process, helping you create a real return on your innovation. It's the next phase in our commitment to update our solution
Page: Dr Marty Hauff
Having received a Bachelor's Degree in Computer and Digital Systems Engineering from RMIT University in 1994, Marty's first engineering jobs saw him designing embedded systems for the high volume automotive market as well as launching an enterprise of his
Page: Drag & Drop Placement from the Vaults Panel
Vaults パネルからドラッグアンドドロップで配置   Placing components and managed sheets from an Altium Vault just got a whole lot easier in Altium Designer 13.2, with the ability to drag & drop revisions of these Item types onto the active schematic document, directly from th
Page: Driving Fabrication Outputs using a Variant
Japanese Previously when defining the output generators in an Output Job file, variants of a design could only be used to drive those outputs which are not fabrication-based. This, by definition, is the very essence of an assembly variant – varying only t
Page: Duplicating an Assembly Variant
You may have defined an assembly variant which includes many changes in relation to the base design. A subsequent assembly variant may be required, which is similar to this existing variant. Rather than adding a new variant and having to 'redo' most of th

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Page: Easy trax
Altium Freeware End-User License Agreement IMPORTANT - READ CAREFULLY This Altium Freeware End-User License Agreement ("EULA") is a legal agreement between you (either an individual person or a single legal entity, who will be referred to in this EULA as
Page: ECAD - MCAD Integration
Chinese Altium's unique ECAD-MCAD integration environment allows designers the opportunity to import whole design concepts and complete their PCB board shape and height/volume restrictions with complete confidence. In effect, a PCB designer can work direc
Page: Editing an Arbiter Component
Configuration aside, there are three 'areas' of the Arbiter component that can be edited: Its location Its ports Its standard component properties, including user-defined parameters. Use the following links to take a closer look at each of these three are
Page: Editing an Interconnect Component
Configuration aside, there are three 'areas' of the Interconnect component that can be edited: Its location Its ports Its standard component properties, including user-defined parameters. Use the following links to take a closer look at each of these thre
Page: Editing Arbiter Component Location
To change the location of an Arbiter component within the workspace, simply click anywhere on the component – away from its ports – and drag to reposition it. The component can be rotated or flipped while dragging. The component's designator and user-defi
Page: Editing Arbiter Component Ports
The OpenBus Editor provides various features and commands for the manipulation of ports with respect to an Arbiter component. The following sections look at the management of ports for a placed Arbiter component – how they can be added and removed, and ho
Page: Editing Arbiter Component Properties
In a Schematic document, all placed objects have an associated properties dialog, typically accessed from the right-click context menu or by double-clicking directly on the object. In an OpenBus System document, there are no such properties dialogs. Viewi
Page: Editing Arcs of Outlines
Some shapes such as polygons and regions - and even 3D body extrusions - can now be created using the same interactive options for creating their outlines as exists in the interactive routing tools. This means that these shapes can be formed using arcs to
Page: Editing Assembly Variants
A selected assembly variant can be edited either by clicking on the Edit Variant button or by choosing the command of the same name from the right-click menu for the dialog. The Variant of [ProjectName] dialog will appear, where you can make changes to ei
Page: Editing Interconnect Component Location
To change the location of an Interconnect component within the workspace, simply click anywhere on the component – away from its ports – and drag to reposition it. The component can be rotated or flipped while dragging. The components' designator and user
Page: Editing Interconnect Component Ports
The OpenBus Editor provides various features and commands for the manipulation of ports with respect to an Interconnect component. The following sections look at the management of ports for a placed Interconnect component – how they can be added and remov
Page: Editing Interconnect Component Properties
In a Schematic document, all placed objects have an associated properties dialog, typically accessed from the right-click context menu or by double-clicking directly on the object. In an OpenBus System document, there are no such properties dialogs. Viewi
Page: Editing Multiple Objects
複数オブジェクトの編集   This section describes various techniques for applying edits to multiple objects in your design. It covers using the Find Similar Objects dialog and Inspector panel combination, as well as the Parameter Manager and the Model Manager. Finally
Page: Editing Multiple Parameters Using the Parameter Manager
Figure 1. Choose which types of parameters to edit User-defined design attributes are added to your design using parameters. Component parameters can be used to define anything from component ratings, to stock information, to PCB component class membershi
Page: Editor Shortcuts
エディタのショートカット   Common Schematic and PCB Editor Shortcuts SHIFT While autopanning to pan at higher speed Y While placing an object to flip it along the Y-axis X While placing an object to flip it along the X-axis CTRL + SHIFT + ↑ ↓ ← → Move selection ten g
Page: Editors, Panels and Object Reference
エディタ、パネルとオブジェクト リファレンス Editors PCB Editor CAM Editor Panels PCB Editor and PCB Library Editor Panels CAM Panels Design Objects The following objects are available for PCB design. Press F1 over a design object for more information. Arc Board Shape Componen
Page: Electrical Rules
Clearance Constraint Short Circuit Unconnected Pin Unrouted Net
Page: EMAC32 - Accessible Internal Registers
The following sections detail the internal registers for the EMAC32 Controller, accessible from the host processor. Receiver Command Register (RX_CMD) Address: 0h Access: Read and Write Value after Reset: 00000000h This 32-bit register is used to control
Page: EMAC32 - Block Diagram
Figure 1 shows a high-level block diagram for the EMAC32 component. Figure 1. EMAC32 block diagram. The internal structure of the Controller consists of a receiver, a transmitter, registers accessible by the Wishbone Slave interface and two distinct dual
Page: EMAC32 - Interrupts
For both the Receiver and Transmitter an interrupt register is available to enable different interrupt sources – RX_INT and TX_INT respectively. For normal use, there is no need for any software intervention while transmitting or receiving packets. Just m
Page: EMAC32 - Memory Layout of Receive and Transmit Buffers
The EMAC32 uses the following generic layout for the Receive and Transmit buffers: Figure 1. Generic layout for Receive and Transmit Buffers. The PACKET_SIZE is a 32-bit word which indicates the length of the next PACKET_DATA in bytes. The PACKET_SIZE is
Page: EMAC32 - Operational Overview
The following sections summarize initialization of the EMAC32 Controller and the steps involved in sending and receiving messages. A section is also included which summarizes the steps required to write to, or read from, the internal PHY device registers.
Page: EMAC32 - Pin Description
The following pin description is for the EMAC32 when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be made
Page: EMAC32 - Wishbone 32-bit Ethernet Media Access Controller
Figure 1. EMAC32 - Wishbone 32-bit Ethernet Media Access Controller. The 32-bit Ethernet Media Access Controller component (EMAC32) is a Wishbone-compliant component providing an interface between a processor and a standard Physical Layer device (PHY) thr
Page: EMAC8_MD_W - Accessible Internal Registers
The following sections detail the internal registers for the EMAC8_MD_W, that can be indirectly accessed from the host processor. Access to these registers is made using dedicated internal Wishbone registers. See Internal Wishbone Registers for more infor
Page: EMAC8_MD_W - Block Diagram
Figure 1 shows a high-level block diagram for the EMAC8_MD_W component. Figure 1. EMAC8_MD_W block diagram. The internal structure of the Controller consists of memory-mapped registers and two distinct dual port RAM blocks, used for the Transmit and Recei
Page: EMAC8_MD_W - Communicating with Internal PHY Registers
The following two sections detail how to write to and read from, an internal register in the connected PHY device respectively, when using the EMAC8_MD_W component.   Only one action – Read or Write – can be started at a time. If you give the command to b
Page: EMAC8_MD_W - Pin Description
The following pin description is for the EMAC8_MD_W when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be
Page: EMAC8_MD_W - Wishbone 8-bit Extended Ethernet Media Access Controller
Figure 1. EMAC8_MD_W - Wishbone 8-bit Extended Ethernet Media Access Controller. The 8-bit Extended Ethernet Media Access Controller component (EMAC8_MD_W) is a Wishbone-compliant component providing an interface between a processor and a standard Physica
Page: EMAC8_W - Accessible Internal Registers
The following sections detail the internal registers for the EMAC8_W, that can be indirectly accessed from the host processor. Access to these registers is made using dedicated internal Wishbone registers. See Internal Wishbone Registers for more informat
Page: EMAC8_W - Block Diagram
Figure 1 shows a high-level block diagram for the EMAC8_W component. Figure 1. EMAC8_W block diagram. The internal structure of the Controller consists of memory-mapped registers and two distinct dual port RAM blocks, used for the Transmit and Receive mes
Page: EMAC8_W - Pin Description
The following pin description is for the EMAC8_W when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be mad
Page: EMAC8_W - Wishbone 8-bit Standard Ethernet Media Access Controller
Figure 1. EMAC8_W - Wishbone 8-bit Standard Ethernet Media Access Controller. The 8-bit Standard Ethernet Media Access Controller component (EMAC8_W) is a Wishbone-compliant component providing an interface between a processor and a standard Physical Laye
Page: EMAC8_W, EMAC8_MD_W - Internal Memory Buffers
The following sections detail the memory buffers used for the Transmit and Receive sections of the Controller. Transmit Buffer Address: 000h to 5EDh Access: Write-only Value after Reset: Unknown The message data to be transmitted is written to and stored
Page: EMAC8_W, EMAC8_MD_W - Internal Wishbone Registers
To simplify communications with internal EMAC registers, and to reduce the number of addresses, all Wishbone communication is carried out through three dedicated registers – the Wishbone Low Address register (WAREG_L), Wishbone High Address register (WARE
Page: EMAC8_W, EMAC8_MD_W - Operational Overview
The following sections summarize the steps involved in sending and receiving messages using the EMAC8_W or EMAC8_MD_W Controllers. Initializing the Controller You will need to re-initialize the Controller, ready for reception of messages, after each exter
Page: Embedded Board Array (Panelize)
エンベデッド ボードアレイ (Panelize)   Description An embedded board array is a primitive design object. It allows you to create a PCB panel (representing the physical board that the PCB is to be manufactured from) as part of your PCB design project. This is also kno
Page: Embedded Breakpoints Panel
Function The Breakpoints panel provides information on all breakpoints that are currently defined - either within the open source code documents for any embedded project or in one of the memory address spaces associated with a processor whose embedded cod
Page: Embedded Call Stack Panel
Function The Call Stack panel provides information about which line of source code the debugger is next going to execute and which function that line of code resides in. If a sequence of function calls have been made to reach the current line of code, the
Page: Embedded Code Explorer Panel
Function The Code Explorer panel provides a visual summary of all identifiers (Define statements, Variables, Routines (functions) or Labels) that are used in the active source document (*.C, *.asm, *.h) for an embedded software project (*.PrjEmb). Content
Page: Embedded Cross References Panel
Function The Cross References panel enables you to quickly locate all occurrences of a variable, function or procedure, within the source code documents of an embedded project. Content and Use Information in the Cross References panel will only appear aft
Page: Embedded Debug Console Panel
Function The Debug Console panel provides a history of the current debug session, in terms of the commands issued and the lines of code executed. The panel also offers command-line debugging of the embedded code. Content and Use As you debug the source co
Page: Embedded Evaluate Panel
Function The Evaluate panel is used to quickly determine the current value of a variable or expression in the active high-level source code document (*.C) currently being debugged. Content and Use Use the field at the top-left of the panel to enter the va
Page: Embedded Processor Memory Panels
Function The various memory panels available for a processor enable you to interrogate the different memory spaces associated to that processor, concurrently. Content and Use The behavior of each of the available memory panels is identical, regardless of
Page: Embedded Registers Panel
Function The Registers panel allows you to interrogate the content of registers within the core processor currently being debugged. You can also change the values of registers on-the-fly as you debug. Content and Use The actual content of the panel, in te
Page: Embedded RTOS Panel
Function The RTOS panel enables you to interrogate the state and operation of the Real Time Operating System, as you debug the active RTOS embedded project. Content and Use When initially opened, the RTOS panel is empty. To populate the panel, first start
Page: Embedded Watches Panel
Function The Watches panel enables you to create and display a list of watch expressions, allowing you to keep track of variable/expression values as you single-step debug the source code of an embedded software project. Content and Use The panel lists, f
Page: Enable Basic Reference
This reference manual describes how to use Enable Basic language to create scripts. The following topics in this Enable Basic Language Reference provide an overview of the structure of a script written in the Enable Basic language: Exploring the Enable Ba
Page: Enabling Pin Swapping on the PCB
Pin swapping is enabled on the PCB side. This is performed using one of the following methods: Access the Configure Swapping Information In Components dialog (Tools » Pin/Part Swapping » Configure), and enable the Pin Swap option for the required componen
Page: Enabling the Soft Devices JTAG Chain
How do I hook up the JTAG chains in my target system? Communications from the Altium Designer software environment to embedded processors and virtual instruments in an FPGA design, is carried out over a JTAG communications link. This is referred to on the
Page: Enhanced Customization of Schematic Ports
強化された回路図ポートのカスタマイズ    Schematic Enhancements  Customization of port objects is taken to a whole new level in Altium Designer 13.0. You now have the ability to control the height of the port and its border width. In addition, the font used for the port nam
Page: Enhanced Devices View
The functionality of the Devices view (View » Devices View) has been greatly enhanced for Altium Designer Winter 09. You can now control exactly what you see, and how you see it. When developing your embedded intelligence, any combination of hardware conn
Page: Enhanced Display of DRC Violations
デザインルール違反表示の強化 PCB Design Rules Visualization  The Summer 09 release extends the use of detailed custom violation graphics to include the majority of design rules that can be checked as part of Online and/or Batch DRC. Complemented through the provision o
Page: Enhanced Footprint Compare and Update
增强的封装比较和更新 Japanese Being able to compare and merge changes to the PCB and it's routing enable design team members - be they one or many - to keep track of design history and collaborate with each other very effectively. It is important to be able to do t
Page: Enhanced Library Management Using Integrated Libraries
統合ライブラリを使用した高度なライブラリ管理   Schematic libraries allow you to attach footprint, simulation and other models to components. Usually, each of these model links references a file somewhere outside of the schematic library. PCB footprints will be found in PCB lib
Page: Enhanced Output Path Definition in Output Job Files
Japanese Output Job Editor Enhancements Ever generated an output from an Output Job file and wondered why it didn't quite end up in the place you thought it would? Ever tried some bizarre workaround to get that pdf in the right folder? Ever been puzzled a
Page: Enhanced PCB Modeling
PCB Texture Mapping Via Stack Ups and Offset Holes The modeling of the PCB within Altium Designer is key to allowing the addition of new features that support building of more sophisticated boards. Winter 09 includes several enhancements to the way that t
Page: Enhanced Polygon Pour Manager
Japanese 增强的多边形铺铜管理器 Enhanced Polygon Manager The Polygon Pour Manager dialog delivers further productivity-enhancements in Altium Designer, providing additional functionality with which to manage all polygon pours for your board. Additional abilities suc
Page: Environment Shortcuts
環境のショートカット F1 Access Documentation Library (in context with object under cursor) CTRL + O Access Choose Document to Open dialog CTRL + F4 Close active document CTRL + S Save current document CTRL + P Print current document ALT + F4 Close Altium Designer C
Page: EP2C35F672C8 - Feature Summary
Figure 1. Altera Cyclone II FPGA<br>(EP2C35F672C8). The EP2C35F672C8 device is a member of the 1.2V Cyclone II family of FPGAs. The Cyclone II provides a low-cost, high-density solution for applications such as those targeted to the consumer electronics i
Page: EP2C35F672C8 - Supported Differential IO Standards
The following table lists the differential I/O standards supported by the EP2C35F672C8 device. Table 1. Supported differential I/O standards. <DIV align="center"><b>I/O Standard</b></DIV> <DIV align="center"><b>Description</b></DIV> LVDS Low-Voltage Diffe
Page: EP2C35F672C8 - Supported Psueudo-Differential IO Standards
The following table lists the pseudo-differential I/O standards supported by the EP2C35F672C8 device. Pseudo-differential outputs involve using two single-ended outputs, with the second inverted. Pseudo-differential inputs simply treat differential inputs
Page: EP2C35F672C8 - Supported Single-Ended IO Standards
The following table lists the single-ended I/O standards supported by the EP2C35F672C8 device. Table 1. Supported single-ended I/O standards. <DIV align="center"><b>I/O Standard</b></DIV> <DIV align="center"><b>Description</b></DIV> 1.5-V LVCMOS Low-Volta
Page: EP2C35F672C8 - Supported Voltage-Referenced IO Standards
The following table lists the voltage-referenced I/O standards supported by the EP2C35F672C8 device. Table 1. Supported voltage-referenced I/O standards. <DIV align="center"><b>I/O Standard</b></DIV> <DIV align="center"><b>Description</b></DIV> HSTL-15 cl
Page: EP3C40F780C8N - Feature Summary
Figure 1. Altera Cyclone III FPGA<br>(EP3C40F780C8N). The EP3C40F780C8N device is a member of the 1.2V Cyclone III family of FPGAs. The Cyclone III provides a low-cost, low-power and high-density solution for applications such as those targeted to the con
Page: EP3C40F780C8N - Supported Differential IO Standards
The following table lists the differential I/O standards supported by the EP3C40F780C8N device. Table 1. Supported differential I/O standards. <DIV align="center"><b>I/O Standard</b></DIV> <DIV align="center"><b>Description</b></DIV> BLVDS Bus Low-Voltage
Page: EP3C40F780C8N - Supported Psueudo-Differential IO Standards
The following table lists the pseudo-differential I/O standards supported by the EP3C40F780C8N device. Pseudo-differential outputs involve using two single-ended outputs, with the second inverted. Pseudo-differential inputs simply treat differential input
Page: EP3C40F780C8N - Supported Single-Ended IO Standards
The following table lists the single-ended I/O standards supported by the EP3C40F780C8N device. Table 1. Supported single-ended I/O standards. <DIV align="center"><b>I/O Standard</b></DIV> <DIV align="center"><b>Description</b></DIV> 1.2-V LVCMOS Low-Volt
Page: EP3C40F780C8N - Supported Voltage-Referenced IO Standards
The following table lists the voltage-referenced I/O standards supported by the EP3C40F780C8N device. Table 1. Supported voltage-referenced I/O standards. <DIV align="center"><b>I/O Standard</b></DIV> <DIV align="center"><b>Description</b></DIV> HSTL-12 c
Page: ESD and the Desktop NanoBoard NB2DSK01
The NB2DSK01 contains many digital devices that are highly sensitive to electrostatic discharge (ESD). To provide a level of protection against such discharge, the NB2DSK01 incorporates shielding for the following metallic-based components that are routin
Page: ESD and the NanoBoard 3000
Related article: Common ESD Prevention Techniques The NanoBoard 3000 contains many digital devices that are highly sensitive to electrostatic discharge (ESD). To provide a level of protection against such discharge, the motherboard incorporates shielding
Page: Ethernet Protocol
The following sections take a look at the Ethernet protocol, including the format of the transmitted data frame, the interframe gap and what happens when frames of data collide during transmission. Data Packaging Format Data is transmitted over the Ethern
Page: Example Designs
Altium Designer includes a comprehensive range of example designs and tutorials that demonstrate the capabilities of the software. There are numerous examples of PCB and FPGA projects, as well as projects that demonstrate various aspects of the software i
Page: Exporting Step From MCADs
This page informs users of different CAD system options or settings to provide when exporting a native document as a *Step AP214* file. In doing so, the resultant Step file can be read into Altium Designer and placed in a PCB document as a source model fr
Page: Exporting to IDF Format through an OutJob File
OutJob ファイルを通して IDF フォーマットへエクスポート   The Intermediate Data Format (IDF) is a format for exchanging printed circuit assembly information between ECAD and MCAD systems. Altium Designer supports the export of your PCB in IDF format, as part of output generati
Page: Extended C-to-Hardware Features
Japanese Related articles: Introduction to C-to-Hardware Compilation Technology in Altium Designer, Tutorial - Designing Custom FPGA Logic using C FPGA designs can be created using a mixture of two techniques – using pre-existing components such as proces

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Page: Fabrication and Assembly Testpoint Style (PCB Design Rules)
Related articles: Testpoint System, Fabrication and Assembly Testpoint Usage The Fabrication Testpoint Style and Assembly Testpoint Style design rules specify the allowable physical parameters of pads and vias that are to be considered for use as testpoin
Page: Fabrication and Assembly Testpoint Usage (PCB Design Rules)
Related articles: Testpoint System, Fabrication and Assembly Testpoint Style The Fabrication Testpoint Usage and Assembly Testpoint Usage design rules specify which nets require testpoints for bare-board fabrication testing or in-circuit assembly testing
Page: Fabrication Outputs
How do I generate manufacturing files The Fabrication Outputs category of the OutputJob Editor allows you to create the following Output Generators: Composite Drill Guides Drill Drawing Guides Final Artwork Prints Gerber Files Solder/Paste Mask Prints NC
Page: Fabrication Testing (PCB)
Related article: Assembly Testing Fabrication testing relates to the testing of a printed circuit board at the pre-assembly phase of manufacture, before any components have been placed onto the board. As such, it is often referred to as bare-board testing
Page: Facilitating Real-Time Debugging of a Processor
To facilitate real-time debugging of a 32-bit processor, the processor must be configured to include JTAG-based On-Chip Debug System (OCDS) hardware. For the following processors, this hardware is permanently installed: CoreMP7 PPC405A For other supported
Page: Fanout and Escape Routes
Chinese Altium Designer includes excellent surface mount component fanout tools, which also support BGA escape routing. The escape routing engine will attempt to route each pad out to just beyond the edge of the device - making routing connections to them
Page: Fanout Control
Specifies fanout options to be used when fanning out the pads of surface mount components in the design that connect to signal and/or power plane nets. Fanout essentially turns an SMT pad into a thru hole pad, from a routing point of view, by adding a via
Page: FAQs & Additional Resources
A useful aide in getting up and running with a particular area of a software solution is to consult a list of frequently asked questions. There just might be an answer to that question you need answering, and which can supply the helping hand to move thro
Page: Favorites Panel
Function The Favorites panel stores and provides easy access to custom views, consisting of position and zoom, of your project documents. Once a view is saved as a favorite, you can call it up at any time from this panel and the view will be loaded into t
Page: Field Servicing using the Viewer Edition of Altium Designer
For a Field Application Engineer, or Service Engineer out in the field, access to the GUI of a Custom Instrument, embedded within an FPGA design, could not be simpler. A trusty laptop computer loaded with the Viewer Edition of Altium Designer is all that
Page: Files Panel
Function The Files panel provides a central area from where you can open existing projects and documents, or create new ones. The panel is divided into the following five regions, each of which can be individually collapsed or expanded by clicking on the
Page: Fill
Description A fill is a primitive design object. It is a rectangular object that can be placed on any layer. When placed on a signal layer, a fill becomes an area of solid copper that can be used to provide shielding or to carry large currents. Fills of v
Page: Finding Differences and Synchronizing Designs
Whether you are transferring a captured design to a new PCB document for the first time, or making changes to an existing design on either the schematic or PCB side, some way of keeping the two sides in-sync is required. Altium Designer provides a powerfu
Page: Fine-Grained Software Locate Control
Japanese Fine-Grained Locate Control In the Summer 09 release of Altium Designer, the Project Options dialog for an embedded project was equipped with the Locate Options tab – providing you with options to determine, with greater control, how each of the
Page: Flight Time- Falling Edge
Description Specifies the maximum allowable flight time on signal falling edge. Flight time is the signal delay time introduced by the interconnect structure. It is calculated as the time it takes for the signal on the net to fall to the threshold voltage
Page: Flight Time- Rising Edge
Description Specifies the maximum allowable flight time on signal rising edge. Flight time is the signal delay time introduced by the interconnect structure. It is calculated as the time it takes to drive the signal on the net to the threshold voltage (ma
Page: Following a Signal Trail - NB2DSK01 Constraint Example
Perhaps the most useful way to illustrate the NB2DSK01 constraint system is by example. To highlight the mapping involved between each constituent part of the system, we will follow the trail of a couple of example signals, related to the video output res
Page: Forum Guidelines and Rules
Parent article: AltiumLive - Forums The AltiumLive Forums play an important role in facilitating a gathering place for the wider AltiumLive community to communicate and share their knowledge. Their very function is to provide an effective arena for fieldi
Page: FPGA Debugging - Peripheral Register View
FPGA 调试 - 外设寄存器视图 FPGA デバッギング - ペリフェラル レジスタ画面 Peripheral Register View Many of the peripheral components available for use in an FPGA design possess internal registers that are accessible by you, the designer. Interaction with these registers is typically
Page: FPGA Design
Japanese How do I create an FPGA design? How do I build an FPGA design? How do I Choose an FPGA Device? FPGA Design for Board Level Designers How do I Target FPGA-specific Resources? How do I Include Pre-generated EDIF in my FPGA Design? How do I Transfer
Page: FPGA SI Tutorial - Checking for Crosstalk
Finally we will look at how to examine the crosstalk between signals. Given that we were able to choose drive and slew settings that minimized ringing on the signals, crosstalk problems should have already been minimized. There are essentially two stages
Page: FPGA SI Tutorial - Setting Up
Before we do any analysis we need to make sure that the components connected to the signals of interest all have the correct models set up. These components are listed below. U1          FPGA – Xilinx XC3S1000-4FG456C U5          PROCESSOR – Sharp LH79520
Page: FPGA SI Tutorial - Simulating the Reflection Characteristics
Now that things are setup we can simulate the reflection characteristics of these signals. Firstly, to analyze the reflection characteristics: Open one of the project documents (either a schematic or the PCB)   Run Tools » Signal Integrity   Click the Con
Page: FPGA-ready Design Components (non-processor)
FPGA 論理デザイン用コンポーネント (プロセッサ未使用時) How do I Create and Share an FPGA Core? How do I use VHDL or Verilog in an FPGA Design? Altium Designer provides a generic set of FPGA macro components – symbolic representations of blocks of functionality that a user desir
Page: FPGA-Specific Constraint - FPGA_CLOCK
Summary:       States that the top level port of the target technology should use a high speed resource. Values:            True, False TargetKind:     Port Define as:       Constraint file entry, Port Parameter Vendors:         Actel, Altera, Xilinx
Page: FPGA-Specific Constraint - FPGA_CLOCK_DUTY_CYCLE
Summary:      Sets the duty cycle of the clock. Values:           Percentage TargetKind:    Port Define as:      Constraint file entry, Port Parameter Vendors:        Actel, Altera, Xilinx
Page: FPGA-Specific Constraint - FPGA_CLOCK_FREQUENCY
Summary:      Sets the desired frequency of the clock, the place and route tool will attempt to achieve this frequency (but they do not guarantee that it will). Values:           Number followed by units. ie 50 Mhz etc TargetKind:    Port Define as:      
Page: FPGA-Specific Constraint - FPGA_CLOCK_PIN
Summary:      States that the top level port is connected to a reserved clock pin on the target device. Values:           True, False TargetKind:    Port Define as:      Constraint file entry, Port Parameter Vendors:        Xilinx
Page: FPGA-Specific Constraint - FPGA_DELAY_MAX
Parent article: Constraint Files - FPGA-specific Constraint Elements Summary: Sets the maximum delay from input port to output port. The place and route tool will attempt not to exceed this delay (but the Vendors do not guarantee this will be the case). V
Page: FPGA-Specific Constraint - FPGA_DELAY_MAX_FROM
Parent article: Constraint Files - FPGA-specific Constraint Elements Summary: Sets the maximum delay from input port to register. The place and route tool will attempt not to exceed this delay (but the Vendors do not guarantee this will be the case). Valu
Page: FPGA-Specific Constraint - FPGA_DELAY_MAX_TO
Parent article: Constraint Files - FPGA-specific Constraint Elements Summary: Sets the maximum delay from register to output port. The place and route tool will attempt not to exceed this delay (but the Vendors do not guarantee this will be the case). Val
Page: FPGA-Specific Constraint - FPGA_DEVICE
Summary:      Specifies the target device Values:           Device specification, as detailed in the Device field of the Choose Physical Device dialog. TargetKind:    Part Define as:      Constraint file entry, Sheet Parameter Vendors:        Altera, Latt
Page: FPGA-Specific Constraint - FPGA_DRIVE
Summary:      Specifies the current strength of a pin in the target device, and may be applied to ports in the top level entity. Values:           Drive current (eg 12mA) TargetKind:    Port Define as:      Constraint file entry, Port Parameter Vendors:  
Page: FPGA-Specific Constraint - FPGA_GLOBAL
Summary:      States that the signal should be kept and use a high speed resource. Values:           True, False TargetKind:    Net Define as:      Parameter in Parameter Set object attached to net Vendors:        Altera, Xilinx
Page: FPGA-Specific Constraint - FPGA_INHIBIT_BUFFER
Summary:      No I/O buffers are inserted at the pin Values:           True, False TargetKind:    Port Define as:      Constraint file entry, Port Parameter Vendors:        Xilinx
Page: FPGA-Specific Constraint - FPGA_IOSTANDARD
Summary:      Specifies the pin IO standard in the target device, and may be applied to ports in the top level entity. Values:           Refer to vendor device documentation TargetKind:    Port Define as:      Constraint file entry, Port Parameter Vendors
Page: FPGA-Specific Constraint - FPGA_KEEP
Summary:      Prevents a particular signal from being optimized. Values:           True, False TargetKind:    Net Define as:      Port Parameter Vendors:        Altera, Xilinx
Page: FPGA-Specific Constraint - FPGA_NOCLOCK
Summary:      Prevents the synthesizer from placing a clock buffer. The synthesizer has the ability to infer clock buffers and add them in automatically. Values:           True, False TargetKind:    Port Define as:      Constraint file entry, Port Paramet
Page: FPGA-Specific Constraint - FPGA_PCI_CLAMP
Summary:      Enables Peripheral Component Interconnect (PCI) compatibility for a pin. Values:           True, False TargetKind:    Port Define as:      Constraint file entry, Port Parameter Vendors:        Altera(Cyclone/Stratix)
Page: FPGA-Specific Constraint - FPGA_PINNUM
Summary:      Specifies the pinout in the target device, and may be applied to ports in the top level entity. Values:           Device pin number, in the format required by the vendor tools TargetKind:    Port Define as:      Constraint file entry, Port P
Page: FPGA-Specific Constraint - FPGA_PULLDOWN
Summary:      Adds a pulldown resistor to an input/output port. Values:           True, False TargetKind:    Port Define as:      Constraint file entry, Port Parameter Vendors:        Xilinx
Page: FPGA-Specific Constraint - FPGA_PULLUP
Summary:      Adds a pullup resistor to an input/output port. Values:           True, False TargetKind:    Port Define as:      Constraint file entry, Port Parameter Vendors:        Altera, Xilinx
Page: FPGA-Specific Constraint - FPGA_RESERVE_PIN
Summary:      Ensures that the place and route tools do not assign this particular pin to a port of your design. Values:           Number of pin to be reserved TargetKind:    Pin Define as:      Constraint file entry Vendors:        Actel, Altera, Xilinx
Page: FPGA-Specific Constraint - FPGA_SLEW
Summary:      Specifies the slew standard in the target device, and may be applied to ports in the top level entity. Values:           Refer to vendor device documentation TargetKind:    Port Define as:      Constraint file entry, Port Parameter Vendors: 
Page: FPGAFlow Processes
This section covers the FPGAFlow processes and their parameters (if any). BrowsePhysicalDevices Description Example Process: FPGAFlow:BrowsePhysicalDevices Configure Description The Configure process can configure a device list, synchronize with hard devi
Page: Freeware downloads
Autotrax DOS Freeware version 1.61 - Complete PCB layout package with output support for printers, pen plotters and Gerber. To install: Download and run the file in the root directory of your hard drive to extract the install program. The install program
Page: Frequency Generator Module
How do I use the Signal Generator instrument? Figure 1. Frequency Generator Module. The Frequency Generator module (CLKGEN) takes a reference clock as its input (time-base) and produces output frequencies that are even divisors of this frequency. By wirin
Page: Front-End Design
Front-End Design The Schematic Editor Schematic Editing Essentials Editing Multiple Objects Using Design Directives in a Schematic Document Using Device Sheets Using Signal Harnesses Snippets Connectivity and Multi-Sheet Design Creating a Multi-channel De
Page: Front-End Design - FAQs
Page: FRQCNT2 - Pin Description
Table 1. FRQCNT2 Pin description. <DIV align="center">Name</DIV> <DIV align="center">Type</DIV> <DIV align="center">Polarity / Bus size</DIV> <DIV align="center">Description</DIV> FREQA <DIV align="center">I</DIV> <DIV align="center">Rise/Fall</DIV> Chann
Page: Full Stackup Definition Available for Vias
Via Stack Ups and Offset Holes As manufacturing technology improves and allows higher trace density, it's become increasingly important to allow land sizes to be set independently for each signal layer. It's now possible in Altium Designer Winter 09 to de
Page: Functional Overview of the DB30 Xilinx Spartan-3 Daughter Board
Figure 1 presents a high-level block diagram of the DB30 Xilinx Spartan-3 daughter board. Figure 1. Xilinx Spartan-3 daughter board (DB30) block diagram.
Page: Functional Overview of the DB31 Altera Cyclone II Daughter Board
Figure 1 presents a high-level block diagram of the DB31 Altera Cyclone II daughter board. Figure 1. Altera Cyclone II daughter board (DB31) block diagram.
Page: Functional Overview of the DB32 LatticeECP Daughter Board
Figure 1 presents a high-level block diagram of the DB32 LatticeECP daughter board. Figure 1. LatticeECP daughter board (DB32) block diagram.
Page: Functional Overview of the DB36 Xilinx Virtex-4 LX Daughter Board
Figure 1 presents a high-level block diagram of the DB36 Xilinx Virtex-4 LX daughter board. Figure 1. Xilinx Virtex-4 daughter board (DB36) block diagram.
Page: Functional Overview of the DB40 Altera Cyclone III Daughter Board
Figure 1 presents a high-level block diagram of the DB40 Altera Cyclone III daughter board. Figure 1. Altera Cyclone III daughter board (DB40) block diagram.
Page: Functional Overview of the DB41 Xilinx Spartan-3AN Daughter Board
Figure 1 presents a high-level block diagram of the DB41 Xilinx Spartan-3AN daughter board. Figure 1. Xilinx Spartan-3AN daughter board (DB41) block diagram.
Page: Functional Overview of the DB42 Xilinx Spartan-3A DSP Daughter Board
Figure 1 presents a high-level block diagram of the DB42 Xilinx Spartan-3A DSP daughter board. Figure 1. Xilinx Spartan-3A DSP daughter board (DB42) block diagram.
Page: Functional Overview of the DB46 Xilinx Virtex-4 SX Daughter Board
Figure 1 presents a high-level block diagram of the DB46 Xilinx Virtex-4 SX daughter board. Figure 1. Xilinx Virtex-4 daughter board (DB46) block diagram.
Page: Functional Overview of the Desktop NanoBoard NB2DSK01
Figure 1 presents a high-level block diagram of the Desktop NanoBoard reconfigurable hardware development platform, the heartbeat of which is the NanoTalk Controller. Motherboard resources are highlighted, as well as an indication of how satellite boards
Page: Functional Overview of the NanoBoard 3000
Related articles: Key Features of the NanoBoard 3000, NanoBoard 3000 - Motherboard Resources The following is a high-level block diagram of the NanoBoard 3000, the heartbeat of which is the Host Controller FPGA (NanoTalk Controller). Motherboard resources
Page: Functional Overview of the NB2DSK-SPK01
Figure 1 presents a high-level block diagram of the Desktop Stereo Speaker Assembly NB2DSK-SPK01. Figure 1. NB2DSK-SPK01 block diagram.
Page: Functional Overview of the PB01 Audio-Video Peripheral Board
Figure 1 presents a high-level block diagram of the PB01 Audio / Video peripheral board. Figure 1. Peripheral board PB01 block diagram.
Page: Functional Overview of the PB02 Mass Storage Peripheral Board
Figure 1 presents a high-level block diagram of the PB02 Mass Storage peripheral board. Figure 1. Peripheral board PB02 block diagram. The same set of base ATA/IDE signals are common to each of the ATA/IDE interfaces, as well as the Compact Flash card rea
Page: Functional Overview of the PB03 USB - IrDA - Ethernet Peripheral Board
Figure 1 presents a high-level block diagram of the PB03 USB - IrDA - Ethernet peripheral board. Figure 1. Peripheral board PB03 block diagram.

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Page: General PCB editing improvements
As part of its ongoing improvement of the PCB editing experience in Altium Designer, a number of new features are being introduced with the Winter 09 release. Improved Rule - Broken Net Constraint
Page: Generating a Custom Bill of Materials
This tutorial describes how to use the Report Manager to set up a Bill of Materials (BOM) report. The manipulation of data and columns and exporting to an Excel template are also covered. Several component reports, such as the Bill of Materials (BOM) repo
Page: Generating a Variant Report
You can generate variant reports directly from the Assembly Variant Management dialog. Two 'levels' of report can be generated - basic or detailed. Variant definition information is available only from the Assembly Variant Management dialog. This informat
Page: Generating an OpenBus Report
The OpenBus System is a clean, efficient representation of your main processor system. While open in Altium Designer, any part of the system can be interrogated, either by hovering over a port, taking a peak at the configuration of a component, or accessi
Page: Generating Manufacturing Outputs - FAQs
Page: Generating Output for an Assembly Variant
Assembly and/or report-based output for a variant is typically generated using an Output Job Configuration file (*.OutJob). Such output includes Schematic Prints, Assembly Drawings and a Bill of Materials. The advantage of using an Output Job file is that
Page: Generation and use of Hardware Functions
When configuring the ASP component, the following two options rank as the most important you will ever need to use: Generate ASP – this option provides the ability to enable or disable generation of hardware-compiled functions. With this option enabled, t
Page: Generic JTAG Device Support
If a third party board contains a physical device that is not supported by the system, the device will appear in the Hard Devices chain of the Devices view (View » Devices View) as a Generic JTAG Device. Figure 1. Generic JTAG<br> device detected in the H
Page: Gerber Output Options
When generating Gerber File output, configuration of output options prior to generation is performed using the Gerber Setup dialog. The Gerber Setup Dialog Each Gerber file corresponds to one layer in the physical board – the component overlay, top signal
Page: Getting Help
Extensive help is available to Altium Designer users, as well as those evaluating, from within the software and online. Knowledge Center Altium Designer includes a powerful online help and documentation system called the Knowledge Center. This system is a
Page: Getting ready to route
Japanese Once the components are positioned on the board, you are ready to start routing. Before launching into Altium Designer's routing features, let's cover the features that will help you manage the routing process. Is it Ready to Route? There is a sa
Page: Getting Started
Altium Designer includes a variety of introductory documents and tutorials to help users get started with the software. All these documents can be accessed through Altium Designer’s Knowledge Center (accessed by pressing F1 in the software) and are also i
Page: Getting Started Tutorial - Adding Virtual Instrumentation to the Mix
Japanese To test the state of internal nodes in the design you can 'wire in' virtual instruments. The 'hardware' portion of the instrument is placed and wired on the schematic like other components, and then synthesized into the FPGA. The interface to eac
Page: Getting Started Tutorial - Capturing the Design
Japanese The first thing we need to do is capture our design within the Altium Designer environment. For our simple design circuit, this will involve adding required components to a schematic sheet and wiring them accordingly. Before we can address the sc
Page: Getting Started Tutorial - Exploring Design Hierarchy
Japanese While the FPGA project file (*PrjFpg) links the various source documents into a single project, the document-to-document and net connective relationships are defined by information in the documents themselves. In a hierarchical design, the design
Page: Getting Started Tutorial - Monitoring the State of Device Pins
Japanese Once the design has been downloaded to the FPGA, the Hard Devices chain can be used to monitor the state of the FPGA pins. This is achieved using the device's associated JTAG Viewer panel (accessible from its instrument panel) set to operate in L
Page: Getting Started Tutorial - Processing the Design
Japanese Once the task of capturing an FPGA-based design is complete, the next logical step is to process the source files. This involves compilation and synthesis of the design, to obtain a source netlist file for input to relevant vendor place and route
Page: Getting Started Tutorial - Targeting the Design to the FPGA Device
Japanese Now we are finished with the capture phase of our design, we need to specify which physical FPGA device we want to use – the target for our design and the end medium into which the design will ultimately be programmed and run. For this tutorial,
Page: Getting Started Tutorial - Verifying the Design
Japanese Before we look at targeting and downloading our design to the intended physical FPGA device, it is a good time to verify the integrity of the design. To do this, we must invoke Altium Designer's powerful Design Compiler. The process of compiling
Page: Getting Started with Altium Designer
Japanese Pierwsze kroki z Altium Designer Within Altium Designer, the F1 and Shift+F1 shortcuts are definitely worth getting acquainted with. Hover the mouse over anything inside Altium Designer - a button, command, panel, or design object, and press F1 f
Page: Getting Started with Collaborative PCB Design
Japanese PCB Layout Collaboration Main article: Collaborative PCB Design Like the idea of collaborative PCB design, where multiple designers can work on the same board at the same time, and bring their results together? Altium Designer brings true collabo
Page: Getting Started with Scripting
This tutorial is designed to give you an overview of how to write scripts using the DelphiScript language supported in Altium Designer. It will outline how to create a script project and to store different scripts in this script project. It also briefly c
Page: Getting Started with the Design Data Management System
Japanese Next Generation Component Management  Next Generation Component ManagementTo provide a system that caters for all aspects of data management – from the humble domain model to the board design itself – Altium implements a Design Data Management mo
Page: Getting Started with the Unified Cursor-Snap System
Japanese Advanced Snap Management Main article: Unified Cursor-Snap System Altium Designer's PCB Editor already had a well-defined grid system – with visible grids, snap grid, component grid, and electrical grid all working to help you efficiently place y
Page: Getting to know your Editor
Right-Click Menus Right-clicking in the main design window will pop-up a menu providing commands to access commonly used features such as Document Options and Preferences, as well as commands that are in context with the object currently under the cursor,
Page: Global Knowledge Repository
In order to capitalize on the global user experience and make it universally available, user expert knowledge about the tool and how it is used needs to be captured in a way that is accurate, relevant, useful and easy to exploit for all. The ultimate obje
Page: Glossary
Introduction to the Software Platform   Organization of the Software Platform   Using the Software Platform Builder   Glossary   Term Definition SPI Serial Peripheral Interface Bus A synchronous serial data link that operates in full duplex mode. Devices
Page: Graphical Display of Power Monitoring Data
Display of power monitoring information in tabular format is good, but a visual representation of the values over time is far more engaging and readable. To this end, the power monitoring facility offers the ability to display the monitored information gr
Page: Graphical Editing of Assembly Variants and Board-Level Annotations
Graphical Editing of Assembly Variants  Graphical Editing of Physical Designators (Board-Level Annotation)  The Summer 09 release of Altium Designer heralds the arrival of graphical editing with respect to assembly variants and board-level annotations. Pe
Page: Graphically Editing an OpenBus System
Once the required components have been placed and linked within the OpenBus System, a range of graphical editing features are available – allowing you to fine-tune the presentation of your system. Port Addition & Removal Rearranging Ports Reshaping Links
Page: Grid Manager (PCB)
Advanced Snap Management Parent article: Unified Cursor-Snap System The <i>Grid Manager</i> dialog. The Grid Manager dialog provides a centralized location from which to define and manage all grids for the active PCB document. The dialog provides all cont

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Page: Handling External Interrupts in an OpenBus System
In the example used in the topic Adding Schematic-based Devices to an OpenBus System Design, interrupt lines from all peripheral devices – those in the OpenBus System and the Infrared Decoder on the schematic sheet – were not used. In OpenBus System - Con
Page: Hardware Acceleration
Hardware acceleration is the concept of enhancing the speed of a design by imparting software processes into hardware. Many computational algorithms that are straightforward to code and debug in software are inherently parallel in nature. Encryption algor
Page: Height
Description Defines height restrictions for components placed within the design. When placement of components in certain regions of the board is particularly height-critical, a height rule can be defined with a scope that targets one or more rooms in the
Page: High Speed Rules
Daisy Chain Stub Length Length Matched Net Lengths Maximum Via Count Parallel Segment Vias Under SMD
Page: Hole Size
Creating Design Rules Design Rules Rule Category: Manufacturing Description Specifies the maximum and minimum hole size for pads and vias in the design. The hole size is the diameter of the hole to be drilled through the pad/via during fabrication. Constr
Page: Hole to Hole Clearance
Creating Design Rules Design Rules Rule Category: Manufacturing Description This design rule ensures checking of manufacturing compatibility of drilled holes. When enabled, it will flag any multiple vias / pads at the same location or overlapping pad / vi
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Page: Hooking the OpenBus System to the Top-Level Schematic
With the OpenBus System defined and configured, the system now needs to be interfaced with the top-level schematic in the FPGA design. This is handled through a sheet symbol placed on the schematic sheet. The sheet entries required to populate the sheet s
Page: How can I replace multiple parts at once?
Replacing multiple parts (or schematic components) in one operation is a useful capability. The method to do it is not particularly obvious, especially where the new part is in a different library to the old part. The solution may depend on what sort of l
Page: How Design Rules are Applied
Different design rules are applied in different situations. Certain rules can be applied as you design, by enabling the online design rule check (DRC) feature. A violation of a rule is flagged as soon as the violation occurs during placement. You may pref
Page: How do I get a snap point in the middle of a circle?
Ever wondered how you can add a snap point to the center of a circle? There are essentially two methods, one neater than the other. Method 1 Add many snap points to the edge of a circle. To add these snap points go to Tools >> 3D Body Placement >> Add sna
Page: How do I navigate in 3D?
The question : "How to I rotate my PCB in the 3D view?" or "Why do I get the error 'Action not available in 3D view' ?" ... often arises. This page has been created to help relieve this issue. In short the key combinations for 3D Navigation without a 3D m
Page: How it Works - Configurations and Constraint Files
All of the three classes of constraints described above are implemented as constraints within constraint files. Constraint filescan contain any number of different constraints, for any of the classes mentioned above. To ensure the most portable FPGA desig
Page: How to import a graphic onto the PCB overlay
PCB Logo Creator Script The Altium Designer Scripting Examples folder, available for download from here, contains an example script, the PCB Logo Creator Script, that will convert an image onto the PCB. Located in the 'Examples\Scripts\Delphiscript Script
Page: Hyperlink Text Support in Schematic Documents
回路図ドキュメントでハイパーリンク テキストをサポート    Schematic Enhancements  In today's globally-connected society, the internet has become an established part of everyday life. Where once a physical document would be used for reference (remember that bookshelf gathering dust

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Page: Identifying OpenBus System Content
The key objective of Altium Designer's OpenBus System feature is to allow a designer to build a processor-based system in a more streamlined and abstract way. Before taking a closer look at how this is achieved, it's a good idea to identify which part of
Page: Identifying Out of Date Vault Items
Out of Date Vault Item の識別   One of the challenges of managing and maintaining any design is identifying items that are out of date. To simplify this process when you are working in a Vault-based design, Altium Designer 13.2 brings a number of subtle but
Page: IEEE 754 Standard - Overview
Before discussing the actual WB_FPU - Wishbone Floating Point Unit peripheral in detail, it is worth spending some time to look at the standard to which the floating-point numbers adhere, the IEEE Standard for Binary Floating-point Arithmetic (IEEE 754).
Page: Impedance
Description Specifies the minimum and maximum net impedance allowed. Net impedance is a function of the conductor geometry and conductivity, the surrounding dielectric material (the board base material, multi-layer insulation, solder mask, etc) and the ph
Page: Impedance-Controlled Routing
With increasing device switching speeds impedance controlled routing has become the hot topic for the digital designer. This article will discuss how you can use Altium Designer's Signal Integrity analysis engine to match component impedances, and the imp
Page: Implementing Design Updates
Design updates/changes are implemented using Engineering Change Orders (ECOs). An ECO simply lists all modifications required to implement changes to one or more design documents, in order to satisfy the synchronization action requested. ECOs are used to
Page: Import FPGA Changes Wizard - Choosing the Configurations to use
If there are multiple compatible configurations in the Stub and/or Master FPGA projects, the next page in the Import FPGA Project Changes Wizard will allow you to choose which configuration to use in each project. Figure 1. Specify which configuration to
Page: Import FPGA Changes Wizard - Choosing the FPGA Project to Import from
The second page of the Import FPGA Project Changes Wizard enables you to choose which FPGA project you wish to import design changes from. Click on the ... button to the right of the FPGA Project to import changes from field to access the Choose FPGA Proj
Page: Import FPGA Changes Wizard - Updating Pin Allocations
The next page of the Import FPGA Project Changes Wizard is used to update pin allocations for the linked signals in the Stub and Master FPGA projects. These are the physical pins on the FPGA device. For each signal, the page shows the physical pin assignm
Page: Import FPGA Changes Wizard - Updating Signal Constraints
The next page of the Import FPGA Project Changes Wizard is used to update signal electrical constraints for the linked signals in the Stub and Master FPGA projects. The electrical characteristics for a signal are defined in the FPGA Signal Manager dialog.
Page: Import FPGA Changes Wizard - Updating Signal Names in the Master FPGA Project
The next page of the Import FPGA Project Changes Wizard is used to match signal names between the Stub and Master FPGA projects. Passing of design changes between projects is only made possible through the linking of corresponding signals. Figure 1. Use t
Page: Important Changes To Altium Designer 6
Changes to release names Altium Designer 6.0 includes a new release numbering scheme as follows: X.y.z.aaaa (for example 6.0.2.5245) <table class="dataTable" width="600" align="center" border="0" cellpadding="10" cellspacing="0"> <tbody> <tr> <th width="1
Page: Importing and Exporting Design Files
デザインファイルのインポートとエクスポート Altium Designer incorporates a wide variety of importer and translator technologies, allowing you to easily import designs originating from previous versions of Altium software, or alternative software packages. To make use of the im
Page: Importing and Exporting Rules
Design rules can be exported from, and imported to, the PCB Rules and Constraints Editor dialog. This allows you to save and load favorite rule definitions between different designs. To export, right-click anywhere within the folder-tree pane of the dialo
Page: Importing the Source Models
Placing A source model can be placed directly into a PCB document at any time. However, it is best done as the PCB document is newly formed. When the blank PCB is ready to accept the schematic capture information, first ensure that you are working on a me
Page: Improved Clearance Rule Handling for Differential Pairs (AD10)
Japanese Enhanced Routing Capabilities Related article: Clearance Rule Sub-Scopes for Differential Pairs Altium Designer 10 includes a beneficial enhancement to clearance rule checking in the PCB Editor – specifically aimed at addressing the issue of clea
Page: Improved Font Editing for Schematic Design Objects
回路図デザインオブジェクトの改善されたフォント編集   Altium Designer 13.0 sees a beneficial improvement to the way in which the font is edited for applicable design objects in Schematic, Schematic Library and OpenBus System documents. A new font control not only provides access t
Page: Improved Handling for Missing Legacy Software Platform Plugin
従来のソフトウェア プラットフォーム プラグインの扱い   When opening a Software Platform document (*.SwPlatform) for an Embedded Software project, and that document was built using an older version of the Software Platform, you will be alerted and asked to confirm the Software Pla
Page: Improved Memory Management
改善されたメモリ管理 A critical part of embedded software development is memory management. The Summer 09 release of Altium Designer brings significant advances in this area, by providing a new methodology for setting up memory in your software systems. New Device
Page: Improved Multithreaded Application Debugging (AD10)
Japanese 改进的多线程应用程序调试(版本10) Altium Designer 10 brings with it a series of improvements to the support for POSIX multithreading – collectively allowing multithreaded applications to be debugged in a far more intuitive, streamlined fashion. Named Threads Th
Page: Improved OpenBus Documents
Signal Harness Interfaces for Components In Altium Designer Winter 09, the use of signal harnesses was extended to FPGA and Core projects. The OpenBus system has taken advantage of this in order to reduce the complexity of the interface exported from Open
Page: Improved performance and less memory
In the Winter '09 release, the 3D graphics engine has been optimized for improved graphics and system performance. The main improvements are: Reduced memory consumption Increased frame rates when zooming/panning/rotating the camera Increased response time
Page: Improved Rule - Acute Angle
Summary The acute angle rule has been significantly improved in the Winter 09 release. Previous versions of this rule performed a simple analysis of track pairs resulting in many false violations being reported whilst also missing common cases caused by n
Page: Improved Rule - Broken Net Constraint
Prior to the winter 09 release of Altium Designer the Broken Net rule created one violation per broken net and listed all connected subnet information often making identification of the break a laborious task. The newly improved rule now creates one viola
Page: Improved Rule - Minimum Copper Width
Summary Some manufacturing rules have been improved to keep up with the changing nature of today's designs. Minimum Copper Width is one of those rules. Previously, the existing minimum width rule operated only at the individual primitive level which occas
Page: Improved SDRAM Controllers (AD10)
Japanese Altium Designer 10 delivers improvements to the SDRAM controller interface, available through the three configurable Wishbone memory controller peripherals – WB_MEM_CTRL, WB_SHARED_MEM_CTRL_NB2DSK01, and WB_SHARED_MEM_CTRL_NB3000. The SDRAM Contr
Page: Inclusion of Not Fitted Components in a BOM
Service Pack 2 (SP2) for the Summer 09 release of Altium Designer brings with it the ability to include, in a generated Bill of Materials, those components that are not fitted on the currently chosen assembly variant. To facilitate this ability, a new opt
Page: Increased Mechanical Layers for Board Design
Additional Mechanical Layers  The Summer 09 release of Altium Designer heralds the arrival of 16 new mechanical layers available for board implementation. This doubles the available layers, bringing the total number of mechanical layers to 32. As with all
Page: Incremental Unroute
連続したアンルート   While in interactive routing mode, should you wish to rip-up and essentially unwind the track you are currently placing, you can do so using the Backspace key. But what about after the track has been laid? Wouldn't it be neat if you could do s
Page: Index
Page: Infrared Communication Concepts
Infrared remote control devices are abundant in today's gadget-filled world. From the television and video recorder, through the Hi-Fi and on to the garage door that thankfully opens remotely on a rainy day, a remote controller of one form or another is n
Page: Installation and Content Management
インストールと Content 管理 Instalacja Altium Designer   Altium Designer - Installation and Management Installation of any software application should be straightforward, intuitive and, perhaps above all, fast – you don't want to be hanging around while an install
Page: Instrument Rack - Hard Devices
Function The Instrument Rack - Hard Devices panel is used to contain and display hard device instruments detected in the Hard Devices chain. Content and Use When the panel is initially opened, it contains no instruments and therefore appears empty. To pop
Page: Instrument Rack - NanoBoard Controller
Function The Instrument Rack - NanoBoard Controllers panel is used to contain and display the NanoBoard Controller instruments associated with NanoBoards detected in the NanoBoard chain. For each instrument displayed, access is provided to the associated
Page: Instrument Rack - Soft Devices
Function The Instrument Rack - Soft Devices panel is used to contain and display soft device instruments detected in the Soft Devices chain. These devices can include processor cores and any of the virtual instruments - frequency generators, frequency cou
Page: Integrated Aldec OEM Simulator
Japanese Aldec OEM Simulator Altium has partnered with Aldec to take Altium Designer's HDL simulation capabilities to a whole new level. Aldec's Advanced VHDL and Verilog Simulation Engine is seamlessly incorporated into Altium Designer as an OEM technolo
Page: Integrated Library Processes
This section covers the Integrated Library processes and their parameters (if any). AddRemoveLibraries Description The AddRemoveLibraries process invokes the Available Libraries dialog allowing you to move up or down the order of installed libraries and a
Page: Integrated Pin Swapping
For better handling of differential pairs while interactively routing, integrated pin (subnet) swapping on the fly has been introduced. The integrated routing command uses pin swapping information available within the project. For example, if you're routi
Page: Interacting with the Desktop NanoBoard NB2DSK01
Altium's Desktop NanoBoard has a touchscreen based interface for loading examples, exploring the file system and controlling how the system works. Not only does the NanoBoard's firmware provide an intuitive user interface for the reconfigurable developmen
Page: Interactive Differential Pair and Multi-trace (Bus) Routing
Two new interactive routing tools have been added for better handling of differential pairs and multi-trace bus routing. Based on the interactive routing engine introduced in Summer '08, similar commands and features make its use intuitive and easy to use
Page: Interactive Net Length Calculation
インタラクティブネット長の計算   For many designs, an important aspect of routing the PCB is knowing the net length. Updated in Altium Designer 13.2, the current net length is available when interactively routing a net, and when interactively modifying an existing route
Page: Interactive Routing - Glossing
Japanese Main article: PCB Routing When we hear the term "gloss" our minds are typically conjuring an image of a beautifully painted object – perhaps the glistening veneer of that luxury automobile you've always dreamed of. In essence, the term reflects a
Page: Interactively Routing a Net
Interactive Routing is more than placing down track objects to join the dots (pads). Altium Designer supports fully featured interactive routing, available via the Place » Interactive Routing command, the button on the PCB Standard toolbar, and the right-
Page: Internal Power and Split Planes
Power planes are special solid copper internal layers, typically used to provide an electrically stable ground or power reference throughout the printed circuit board. This article investigates using internal power and split planes. Plane Basics The PCB E
Page: Interrogating Violations
Chinese There are essentially three methods of interrogating design violations - from the Messages panel, from the PCB panel and directly within the design workspace. The first method is solely associated with having run a Batch DRC. From the Messages Pan
Page: Introduction to C-to-Hardware Compilation Technology in Altium Designer
Japanese Altium Designer features powerful C-to-Hardware Compilation (CHC) technology. At the heart of this technology is the C-to-Hardware Compiler. The Compiler takes C source code as input and produces FPGA logic as output. Altium Designer's integrated
Page: Introduction to the Query Language
Underlying Altium Designer's schematic and PCB editors is a powerful query engine. By entering queries into this engine you can filter down to find and edit precisely those objects you require. Perhaps the greatest challenge when working on a complex elec
Page: Introduction to the Software Platform
Japanese Introduction to the Software Platform   Organization of the Software Platform   Using the Software Platform Builder   Glossary   The Software Platform is a software framework to facilitate writing software to access peripherals on your hardware d
Page: IPC® Compliant Batch Footprint Generator Reference
This reference provides technical information on configuring and using the IPC® Compliant Footprints Batch Generator to generate IPC compliant footprints in a PCB library document. Building IPC compliant footprints from datasheet package information files
Page: Item Lifecycle Management
Item ライフサイクル管理 The revision reflects the progress of the Item as it undergoes design changes. Or to say that the other way around, if the design changes, the revision must be incremented to reflect that. For any revision of an Item, it may also be importa
Page: Item Manager
Item Manager   The Item Manager is a powerful tool providing two key abilities in relation to components and sheets of re-usable schematic circuitry in a board design project: Migration – firstly, it facilitates the migration of a design project from usin
Page: Item Revision Naming Schemes
Item レビジョン Naming Scheme   Parent article: Items and Item Revisions The Item ID is the unique name, or identifier, you give to each Item you want to be able to release. Any Item may well change through the course of its life though, it might be due to des
Page: Items and Item Revisions
Japanese The tangible object that is made from a design project and sold by a company is manufactured from a specific set of data, generated from source design files. The data used for manufacturing can be thought of as the set of instructions used to bui
Page: ITU-R BT.656 Protocol
The BT.656 video signal data format was introduced formally as a recommendation from the Radiocommunication sector of the International Telecommunication Union (ITU-R). It describes a simple protocol for the interfaces and data stream format required to s

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Page: JScript Reference
The JScript reference describes the JScript scripting language used in Altium Designer. Exploring the JScript Language This Reference details each of the JScript Scripting statements, functions and extensions that are supported in the scripting system. Th
Page: JTAG Chains in the System
When a design is created and downloaded to the physical FPGA device – resident on the daughter board currently plugged into the NanoBoard – several JTAG chains are created to facilitate communications between the various devices within the system. Within
Page: JTAG Channel Mapping
The defined mappings in a JTAG Board file use bit masks. Table 1 summarizes each of the mask values that can be used and how these values relate to the pins of the parallel port. Table 1. DB25 Parallel Port Mapping - mask values. <DIV align="center"><b>Ma
Page: JTAG Overview
Back in 1985 in response to the increasing density of then new electronics packaging technologies, test engineers from the major silicon vendors in Europe formed the Joint European Test Action Group and set about forming proposals for a new way of testing

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Page: Keeping Components Up-To-Date
This document provides detailed information on updating placed components with changes made to those components in source libraries or a linked external database. You've placed your components on the schematic, maybe even fully wired, compiled and taken t
Page: Key Features of the Desktop NanoBoard NB2DSK01
Altium's Desktop NanoBoard NB2DSK01 has the following features: Altium NanoTalk parallel PC interface Altium NanoTalk USB 2.0 PC interface NanoTalk Master and Slave connectors, 10-way Host status LEDs Xilinx Spartan-3 (XC3S1500-4FG676C) NanoTalk Controlle
Page: Key Features of the NanoBoard 3000
Related articles: Functional Overview of the NanoBoard 3000, NanoBoard 3000 - Motherboard Resources Altium's NanoBoard 3000 has the following features: Host (NanoTalk) Controller FPGA:   NanoBoard 3000XN – Xilinx variant: A Xilinx Spartan-3AN device (XC3S
Page: Key Features of the NB2DSK-SPK01
Altium's Desktop Stereo Speaker Assembly NB2DSK-SPK01 has the following features: Dual 4Ω speakers providing enhanced stereo sound   Output volume controlled by the DC Volume control on the NB2DSK01 motherboard   Six 5mm RGB LEDs   Turned ON/OFF via inter
Page: KEYPADA_W - Accessible Internal Registers
The following sections detail the internal registers for the KEYPADA_W, accessible from the host processor. Key Register (KEYREG) Address: 0 Access: Read Only This register is used to store the 4-bit value representing the key that has been pressed on the
Page: KEYPADA_W - Block Diagram
Figure 1 shows a high-level block diagram for the KEYPADA_W component. Figure 1. KEYPADA_W block diagram. In the block diagram of Figure 1, only the connection of the KEYREG register output to the DATA_O line has been shown, whereby the 4-bit value Key (r
Page: KEYPADA_W - Host to Controller Communications
Communications between a 32-bit host processor and the KEYPADA_W Controller are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycle involved between Host and Controller for reading from the accessible inter
Page: KEYPADA_W - Operational Overview
Operation of the Keypad Controller within a design is very straightforward. The processor to which the Controller is connected simply monitors the INT_O output from the Controller. When the INT_O signal goes High – corresponding to a valid key being press
Page: KEYPADA_W - Pin Description
The following pin description is for the KEYPADA_W when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals to the ke
Page: KEYPADA_W - Wishbone Keypad Controller
Figure 1. KEYPADA_W - Wishbone Keypad Controller. The Keypad Controller component (KEYPADA_W) provides a simple interface between a host processor and a 16-key (4Row x 4Column) keypad, such as that located on the NanoBoard-NB1. The Controller is fully syn

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Page: LAX - Pin Description
The default look of the LAX as it is placed from the library, it must be configured to suit your design requirements. The table below summarizes the function of each of the pins available for the device. The actual pins present on the symbol will depend o
Page: Layer Pairs
Creating Design Rules Design Rules Rule Category: Manufacturing Description Checks to ensure that the used layer-pairs match the current drill-pairs. The used layer-pairs are determined from the vias and pads found in the board, one layer-pair for each St
Page: Leader Dimension
Angular Dimension Baseline Dimension Center Dimension Datum Dimension Linear Dimension Linear Diameter Dimension Radial Dimension Radial Diameter Dimension Standard Dimension Description A leader dimension is a group design object. It allows for the label
Page: Legacy Downloads
  Freeware downloads Autotrax DOS Freeware version 1.61 - Complete PCB layout package with output support for printers, pen plotters and Gerber. To install: Download and run the file in the root directory of your hard drive to extract the install program.
Page: Legacy Downloads for P-CAD
P-CAD 2006 P-CAD 2006 Service Pack 2 (29.7 MB)P-CAD 2006 Service Pack 2 (SP2) includes over 80 features and enhancements, further strengthening system performance and delivering increased stability. To install the SP2 update, you will require the installa
Page: Legacy Libraries
Libraries available from this page have been superseded by later versions. They are retained here, rather than scrapped, as they contain obsolete component models that are not present in the later versions; and these components may be still be of value in
Page: Length
Description Specifies the minimum and maximum lengths of a net. Constraints Minimum the value for the minimum permissible length of the net. (Default = 0mil). Maximum the value for the maximum permissible length of the net. (Default = 100000mil). Rule Cla
Page: LFECP33E-3FN672C - Feature Summary
Figure 1. LatticeECP FPGA (LFECP33E-3FN672C). The LFECP33E-3FN672C device is a member of the 1.2V ECP family of FPGAs. The ECP provides a low-cost, high-density solution for applications such as those targeted to the consumer electronics industry. The ent
Page: LFECP33E-3FN672C - Supported Differential IO Standards
The following table lists the differential I/O standards supported by the LFECP33E-3FN672C device. Table 1. Supported differential I/O standards. <DIV align="center"><b>I/O Standard</b></DIV> <DIV align="center"><b>Description</b></DIV> BLVDS Bus Low-Volt
Page: LFECP33E-3FN672C - Supported Single-Ended IO Standards
The following table lists the single-ended I/O standards supported by the LFECP33E-3FN672C device. Table 1. Supported single-ended I/O standards. <DIV align="center"><b>I/O Standard</b></DIV> <DIV align="center"><b>Description</b></DIV> HSTL15 Class I Hig
Page: Libraries - PCB-related links
Associations: EIA IEEE IPC JEDEC Catalogues: Digi-Key Farnell RS Other Links: Electronic Engineer's Master Online IPC Calculator PCBstandards UltraCAD Design
Page: Libraries Panel
Function The Libraries panel enables you to browse through and place components/footprints from, the available libraries for the active project. Content and Use The top drop-down field in the panel lists the available libraries for the active project. It
Page: Library and Component Management
Japanese Altium Designer provides comprehensive component data management and information resources that allow you to maintain control over parts usage, regardless of the size or demands of your organization. Vault-Based Components Component, Model and Li
Page: Library Query Functions
This section covers Library Query functions used by the Query System in Altium Designer. Comment Field Description Returns all Library Component objects having a Comment property that complies with the Query. Note: The child objects of these Component obj
Page: Library Search Improvements
The library search interface has been greatly simplified to allow for quicker and more efficient queries. The new simplified interface allows you to build simple queries with a few mouse clicks. It searches in the installed libraries for valid parameters
Page: License Service Setup Guide
This guide gives an overview of installing and setting up an Altium Designer Floating License configuration. The Floating License allows multiple instances of Altium Designer to be licensed from a central Floating License Server. Refer to the Altium End U
Page: Licensing and the NanoBoard
Japanese Main articles: NanoBoard NB2, NanoBoard 3000 Series A 12-month subscription to the Soft Design licensing option of Altium Designer is included, in the box, with each Altium NanoBoard. The Soft Design licensing option provides access to functional
Page: Licensing System - FAQs
License types License availability, selection and configuration Using an On-Demand License     On-Demand mode     Roaming mode     Working offline     Releasing a license remotely     Converting to a Standalone license Using a Standalone License     First
Page: Linear Diameter
Angular Dimension Baseline Dimension Center Dimension Datum Dimension Leader Dimension Linear Dimension Radial Dimension Radial Diameter Dimension Standard Dimension Description A linear diameter dimension is a group design object. It allows for the dimen
Page: Linear Dimension
Angular Dimension Baseline Dimension Center Dimension Datum Dimension Leader Dimension Linear Diameter Dimension Radial Dimension Radial Diameter Dimension Standard Dimension Description A linear dimension is a group design object. It places dimensioning
Page: Linked FPGA-PCB Project Changes - Adding a Port to the FPGA Project
There may be occasions when it is decided an additional port is required for an FPGA design. The process begins by adding the port to the top-level source schematic sheet in the FPGA project and connecting it as necessary within the design. Figure 1. Addi
Page: Linked FPGA-PCB Project Changes - Changing FPGA Devices
At some point during the design process, it is quite possible that the desired target FPGA device may change. A larger device might be required or a decision to change vendors might be made. As a first step, the process outlined in Automatically Linking F
Page: Linked FPGA-PCB Project Changes - Changing FPGA Port Names
If a port name is changed within an FPGA project, or a net label for a pin of the FPGA component in the PCB project is renamed, the FPGA Workspace Map dialog will display the Schematic-FPGA Project link as unsynchronized. This is due to the fact that it i
Page: Linked FPGA-PCB Project Changes - Configuring IO Standards
FPGA devices generally support a range of I/O standards. These standards follow industry specifications and often include options like LVTTL, LVCMOS and PCI to name a few. This enables the FPGA to communicate directly with other devices requiring a certai
Page: Linked FPGA-PCB Project Changes - Pin Swapping in both PCB and FPGA Projects
It may be that pin changes have been made in both the PCB project and FPGA project without a synchronize occurring. If this is the case, entering the FPGA Workspace Map dialog will show the Schematic-FGPA Project link out of date (Red). Clicking on the li
Page: Linked FPGA-PCB Project Changes - Pin Swapping in the FPGA Project
Pin swaps initiated from the FPGA project are likely to be required when a design no longer fits within the FPGA device. The design may fit however, if existing pin constraints are relaxed and the vendor tools are permitted to assign various pin numbers.
Page: Linked FPGA-PCB Project Changes - Pin Swapping in the PCB Document
How do I use FPGA Pin Swapping during PCB layout? The net (or port)-to-physical pin assignments for an FPGA device are defined in a constraint file. You can manually define the assignments, or let the place and route tools assign them and then import the
Page: Linked FPGA-PCB Project Changes - Removing a Port from the FPGA Project
You may find that a particular port is no longer required in the design and is subsequently deleted from the FPGA project. There may be existing constraints associated with this port which can be deleted from the constraint file if desired. However, this
Page: Linking a Simulation Model to a Schematic Component
Altium Designer provides a powerful mixed-signal circuit simulator, enabling you to thoroughly analyze a circuit - not only observing its behavior, but also ensuring that it operates within specific design constraints. To simulate a design successfully, a
Page: Linking an FPGA Project to a PCB Project
How do I link and sync my FPGA and PCB projects? Quite often an FPGA-based design, and the design of the board upon which the physical FPGA device will be placed, are worked on in parallel. Alternatively, only the FPGA project may exist, having been devel
Page: Linking Existing Components to Your Company Database
コンポーネントを会社のデータベースへリンク   This document provides detailed information on linking existing Altium Designer components to an external database using Altium Designer's database link feature. Linking between schematic library components and an external database
Page: Live Drill Drawing Table
Live Drill Drawing Table   A standard element required for manufacture of a Printed Circuit Board is a drill drawing table, also known as a drill table or a drill drawing legend. The drill table lists the size and number of holes for each drill used on th
Page: Live Links to Supplier Data
Linking to Supplier's Data Pass by the desk (or glance at a shelf) of any electronics designer/engineer and you will typically find one or more catalogs for parts and components available from 'favored' suppliers. Key to any design is the search for these
Page: Live Supplier Data - BOM Generation
Main article: Live Links to Supplier Data Being able to cost a project and determine the quantities of design components to be ordered from suppliers/distributors, is an essential part of the overall design process. Once you have added the required live S
Page: Live Supplier Data - Currency Conversion
Pricing information is an inherent part of the data available using Altium Designer's Live Links to Supplier Data feature. Different suppliers operate in different, often multiple, regions of the world and, as such, it is common to see product pricing rep
Page: Live Supplier Data - Import to Libraries and Schematics
For any given Supplier Item found through a search in the Supplier Search panel, you can import its parameters, data sheet links, pricing and stock information, as parameters of a target library component (SchLib, DbLib, SVNDbLib), or placed component on
Page: Live Supplier Data - Managing Supplier Links
At the heart of Altium Designer's Live Links to Supplier Data feature is the Supplier Link. This fundamental entity provides the live link between an Altium Designer component and an item in a supplier's database of electronic components. Creation of a Su
Page: Load & Save PCB Layer Details
The "CopyPCBLayerDetails" script makes it easy to save and load the PCB layer names and colours to (from) a file on disk. Download Version 0.1 CopyPCBLayerDetails_V01.zip Forum Discussion See Save Layer settings on the Altium Designer forum for discussion
Page: Logic Analyzer
How do I setup and use the LAX instrument? <div class="panel" style="padding:5px 10px;margin:0 20px 1em 1em;float:right;width:394px;clear:both"> <img src='/download/attachments/3080414/Lax_Configurable65.png'><br> <font size="1"><i>An example of the confi
Page: Logic Analyzer Panel
Function Main article: Logic Analyzer The LAX panel allows you to view the data captured by a Logic Analyzer instrument. It is also used to configure triggering and other Capture Control options. Notes The panel for a Logic Analyzer (LAX) device will be a
Page: Loop Removal Support for Multi-Route Tools (AD10)
Japanese Enhanced Routing Capabilities Related article: Modifying Existing Routing Altium Designer provides support for Loop Removal when routing using either the Multi-Trace or Differential Pair interactive routing tools. As you route there will be many

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Page: Maintaining Design Portability
Designs that are created within the system have a high degree of portability, allowing them to be retargeted to different device and board environments with the minimum of difficulty. This portability is achieved by a combination of: Designing with generi
Page: Managed Schematic Sheets
Japanese Being able to re-use design content is something that all product development companies want, and can greatly benefit from. Not only does reuse save time, being able to easily re-use a section of a previous design means that all the qualification
Page: Managing Altium Designer Preferences
Japanese Altium Designer allows you to transfer your settings between instances of Altium Designer using the Save and Load features of the Preferences dialog. All preferences can be loaded, or you can choose a subset of settings to load. You also have the
Page: Managing Design Changes between Linked Projects
The FPGA Workspace Map dialog gives you the ability to check the state of the design across linked FPGA and PCB projects and the means to propagate design changes between the two. The following sections consider some of the more common design changes that
Page: Managing Design Changes using a Stub FPGA Project
It is often the case that the PCB and FPGA projects are not designed by the same person. Indeed, they might not be developed on the same computer or even in the same locale. In such cases, a method of passing design changes between projects is needed, whe
Page: Managing Design Variation with Variants
Japanese Product requirements may warrant the need to produce a variety of similar Printed Circuit Boards that all differ slightly from an underlying base design. For example, standard and deluxe versions of a commercial electronic product may differ in t
Page: Managing the Item's Revision and Lifecycle State - the Item View
Japanese The backbone to Altium Designer's design data management capabilities is the vault that stores your precious data. An Altium Vault can store a broad variety of data, including: components (and their models); managed content (such as templates and
Page: Manual FPGA-PCB Linking - Detection of the FPGA Component on the Schematic Sheet
The FPGA Workspace Map dialog is used to maintain synchronicity between linked PCB and FPGA projects. Access to this dialog is provided by choosing the command of the same name from the Projects menu, or by pressing the button on the Projects panel. Figur
Page: Manually Linking FPGA and PCB Projects
The PCB project to which the FPGA design project will be linked can of course be created manually and, quite often, this will be the case, with both projects being designed in parallel. In such cases, there may not be an auto-generated schematic sheet for
Page: Manually Linking the FPGA Component Schematic to the FPGA Project
Linking of the two projects is carried out from within the Projects panel. With the panel focused, enable the Structure Editor option. The hierarchical structure within the two separate projects will be reflected in the panel. The entries that appear in t
Page: Manufacturing Rules
Minimum Annular Ring Acute Angle Hole Size Layer Pairs Hole to Hole Clearance Minimum Solder Mask Sliver Silkscreen Over Component Pads Silk to Silk Clearance Net Antennae
Page: Mapping the FPGA Design to the Device Pins
How do I target and constrain an FPGA design? How do I setup FPGA IO? Exploring my Deployment Options How do I use Altium Designer with a Third Party FPGA Development Board? How do I Hook up the JTAG Chains in my Target System? How do I Link and Sync my F
Page: Mapping the FPGA Project to a PCB
Implementing a design into an FPGA on a PCB is done in the Devices view. Here the FPGA project, in combination with a configuration, is targeted to a board. An example is shown in Figure 1. Figure 1. The one FPGA project (RateController), targeted to diff
Page: Mask Rules
Paste Mask Expansion Solder Mask Expansion
Page: Matched Net Lengths
Description Specifies the allowable difference in net lengths. The set of nets targeted by the scope of the rule (as defined by its full query) are interrogated, with the length of each being compared to that of the longest net in the set. Those nets that
Page: Maximum Via Count
Description Specifies the maximum number of vias permitted in the current design. Constraints Maximum Via Count the number of vias allowed in the design. (Default = 1000). Rule Classification Unary How Duplicate Rule Contentions are Resolved All rules are
Page: Memory Instrument
Memory Instrument  The Summer 09 release of Altium Designer sees the introduction of a new memory instrument (MEMORY_INSTRUMENT). This instrument provides an area of configurable memory – located within the instrument itself – with the ability to view and
Page: Mentor Expedition Importer
Japanese Installing and Running the Importer Altium Designer can import binary format PCB and PCB Libraries designed in Mentor Expedition®. To do so: Install the Importer plugin in Altium Designer (DXP » Plug-ins and Updates, Importers and Exporters categ
Page: Messages Panel
Function Whether compiling a project, running a design rule check for the active PCB document, performing a mixed signal simulation, or using any of the other message-enabled features of the software, the Messages panel provides an intelligent way of list
Page: MicroBlaze Data Organization
Data organization refers to the ordering of the data during transfers. There are two general types of ordering: BIG ENDIAN – the most significant portion of an operand is stored at the lower address LITTLE ENDIAN – the most significant portion of an opera
Page: MicroBlaze Interrupts
The 32 external interrupt input signals that can be wired to the MicroBlaze wrapper's Peripheral I/O Interface (the interface of the wrapper around the processor) are connected internally to the MicroBlaze's actual Interrupt port. The Xilinx Interrupt Han
Page: MicroBlaze Memory Space
The MicroBlaze uses 32-bit address buses providing a 4GByte linear address space. All memory access is in 32-bit words, which creates a physical address bus of 30-bits. Memory space is broken into three main areas, as illustrated in Figure 1. Figure 1. Me
Page: MicroBlaze Pin Description
The pinout of the MicroBlaze has not been fixed to any specific device I/O – allowing flexibility with user application. The MicroBlaze contains only unidirectional pins (inputs or outputs).   The following pin description is for the processor when used o
Page: Minimum Annular Ring
Creating Design Rules Design Rules Rule Category: Manufacturing Description Specifies the minimum annular ring required for a pad or via. The annular ring is measured radially, from the edge of the pad/via hole to the edge of the pad/via. Constraints Mini
Page: Minimum Solder Mask Sliver
Creating Design Rules Design Rules Rule Category: Manufacturing Description Minimum Solder Mask Sliver helps identify narrow sections of solder mask that may cause manufacturing problems later. Ensuring that there is a minimum width of solder mask across
Page: Model Linkage Mechanics
Before looking at the various components available to implement the hardware in your FPGA design, it is worth taking a moment to explore just how vendor-independency is achieved in Altium Designer. EDIF models included with the system for the generic, FPG
Page: Modifying Components and Component Parameters for an Assembly Variant
Varying Components for an Assembly Variant In some cases, the components used in an assembly variant may need to be changed in some way. For example, product requirements might dictate that logic functionality should be faster in an enhanced-speed version
Page: Modifying Existing Routing
Routing is probably the most iterative process you perform designing a board, constantly defining and re-defining connection paths as the board layout evolves. This iterative nature requires routing modification tools that compliment the interactive routi
Page: Monitoring the State of Device Pins - Live
Once the design has been downloaded to the FPGA, the Hard Devices JTAG chain can be used to monitor the state of the FPGA pins, in real-time. This is achieved using the device's associated JTAG Viewer panel (accessible from its instrument panel), set to o
Page: Moving from another Design Tool
Japanese How do I import old designs The following links provide Design Tool Specific Information to help you move to Altium Designer: Cadence Allegro® PCB Editor Mentor Graphics® DxDesigner® OrCAD® PADS® Layout™ and OrCAD® Capture™ PADS® Logic™ and PADS®
Page: Moving to Altium Designer from Cadence Allegro PCB Editor
Cadence Allegro PCB エディタから Altium Designer へ移行 The translation of Cadence® Allegro® Design files can be handled by Altium Designer's Import Wizard. Complete flexibility is found in all pages of the wizard, giving you as little or as much control as you wo
Page: Moving to Altium Designer from Mentor Graphics DxDesigner
Mentor Graphics DxDesigner から Altium Designer へ移行 Many DxDesigner® users use a combination of PADS Layout® for their PCB layout, and DxDesigner for their schematic capture. This application note assumes this combination. Getting Started - Transferring You
Page: Moving to Altium Designer From OrCAD
OrCAD から Altium Designer への移行 Translating complete OrCAD® designs, including Capture™ schematics, Layout™ PCB files, and library files can all be handled by Altium Designer's Import Wizard. The Import Wizard removes much of the headache normally found wit
Page: Moving to Altium Designer From P-CAD
Translating complete P-CAD designs, including schematics, PCB layout, and library files can all be directly handled by Altium Designer's Import Wizard without converting to ASCII first - thus avoiding the need for having P-CAD installed. The Import Wizard
Page: Moving to Altium Designer from PADS Layout and OrCAD capture
PADS Layout や OrCAD capture から Altium Designer へ移行 Many PADS® users use a combination of PADS Layout® for their PCB layout and OrCAD Capture™ for their schematic capture. This application note assumes this combination. Getting Started - Transferring Your
Page: Moving to Altium Designer from Pads Logic and PADS Layout
Pads Logic や PADS Layout から Altium Designer へ移行   Translating complete PADS® Logic™ and PADS® Layout™ designs, including PCB, Schematic files and library files can all be handled by Altium Designer's Import Wizard. Import Wizard PADS ASCII Design and Libr
Page: Moving to Altium Designer from Protel 99 SE
Protel 99 SE から Altium Designer へ移行 Protel 99 SE uses the design database, or DDB, to store design files. Altium Designer stores files on the hard drive and now include the concept of the Project. The 99SE Import Wizard gives control and visibility over t
Page: Multi-Channel Design Concepts
Japanese Altium Designer introduces a robust multi-channel design system that even supports channels nested within other channels. Many designs contain repeated circuitry. One board might duplicate the same section thirty-two times, or perhaps contain fou
Page: Multi-Repository Support (Software Platform)
The Software Platform technology in Altium Designer provides a wide range of functionality for electronic systems development. This functionality is currently supplied through use of plugins delivered with the software as part of installation. With the Su
Page: Multi-Sheet and Multi-Channel Design
Altium Designer offers true multi-channel design functionality such as handling of common and distributed nets among channels, naming conventions, and PCB rooms and classes for each channel. Multi-channel designs allow you to reference single sheets in yo

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Page: NanoBoard 3000 - ADC Interface
Analog-to-digital conversion on the NanoBoard 3000 is provided by a 4-channel, 8-bit ADC device – an ADC084S021 from National Semiconductor. This device uses successive-approximation with an internal track-and-hold circuit. The device is powered from a re
Page: NanoBoard 3000 - Audio CODEC
As part of its high-quality audio sub-system, the NanoBoard 3000 provides a CS4270 24-bit, 192kHz stereo audio CODEC (from Cirrus Logic). The CODEC caters for both analog and digital audio I/O. CS4270 Stereo Audio CODEC device. Device Power and Reset Powe
Page: NanoBoard 3000 - Audio System
The NanoBoard 3000 provides a high-quality audio sub-system, complete with analog mixer, power amplifier and various sound output methods. The following sections take a closer look at the various stages involved in the implementation of this system. Sound
Page: NanoBoard 3000 - Board Communications
Communications between the various devices within the system makes extensive use of the technology defined by IEEE Standard 1149.1 – commonly referred to as JTAG. The NanoBoard 3000 is connected to your PC using a USB connection. When you start Altium Des
Page: NanoBoard 3000 - Board ID Memory
Board identification is handled courtesy of a DS2502 1024-bit, 1-Wire EPROM device (from Maxim). The DS2502 is primarily used to contain a code with which to identify the motherboard. It is also used to contain additional information such as revision, rel
Page: NanoBoard 3000 - Buzzer Signal
As part of its audio capabilities, the NanoBoard 3000 provides a hardwired path for a mono-based audio signal from the User FPGA. This signal – a legacy NB1-style Buzzer signal – can be incorporated as input to the board's analog audio mixer.   The Buzzer
Page: NanoBoard 3000 - Common-Bus Flash Memory
The NanoBoard 3000 includes Flash memory as part of the common-bus block of memory resources available to the on-board User FPGA device, or more specifically a programmed design therein. Common-bus Flash memory available to an<br>FPGA design. The Flash me
Page: NanoBoard 3000 - Common-Bus SDRAM
The NanoBoard 3000 includes Synchronous Dynamic RAM as part of the common-bus block of memory resources available to the on-board User FPGA device, or more specifically a programmed design therein. Common-bus SDRAM available to an FPGA design. The SDRAM i
Page: NanoBoard 3000 - Common-Bus SRAM
The NanoBoard 3000 includes Static RAM as part of the common-bus block of memory resources available to the on-board User FPGA device, or more specifically a programmed design therein. Common-bus SRAM available to an FPGA design. The SRAM is provided in t
Page: NanoBoard 3000 - Configuring an FPGA Project Automatically
Main article: Understanding the NanoBoard 3000 Constraint System Although an FPGA design project targeting the NanoBoard 3000 can be configured manually – by adding a configuration, assigning the required board constraint files and creating a mapping cons
Page: NanoBoard 3000 - DAC Interface
Digital-to-analog conversion on the NanoBoard 3000 is provided by a 4-channel, 8-bit DAC device – a DAC084S085 from National Semiconductor. The device delivers rail-to-rail output voltage swing (0V up to a supplied reference voltage) with a maximum zero c
Page: NanoBoard 3000 - Diagnostics Interface
To facilitate board testing using automated test equipment, the NanoBoard 3000 provides a diagnostics ATE interface, courtesy of a PCI Express (PCIe) edge connector. PCIe connector - providing<br>access by external automated<br>test equipment. The connect
Page: NanoBoard 3000 - Ethernet Port
The NanoBoard 3000 provides a fast Ethernet connection, supporting 10Base-T and 100Base-TX, for operational speeds of up to 10Mbps and 100Mbps respectively. An 8P8C ('RJ45') modular connector is used to provide the Ethernet port (a KMFC0901238, from Konve
Page: NanoBoard 3000 - Firmware Updates
NanoBoard 3000 - uaktualnianie firmware'u Main article: NanoBoard 3000 Series Each 3000-series NanoBoard uses an FPGA device as the controller for the board. Referred to as the Host FPGA, or NanoTalk Controller, this device (designated U30) communicates w
Page: NanoBoard 3000 - Generic User Switches
The NanoBoard 3000 provides a further five push button style switches that are wired to separate I/O pins of the User FPGA. They can be used as generic switch inputs to a design. PDA-style push buttons. Each switch is of type SPNO – Single Pole Normally O
Page: NanoBoard 3000 - Host Controller Configuration Flash Memory
Japanese The NanoBoard 3000 has been designed so that the firmware can be updated in the field, over the standard PC-NanoBoard USB connection, without the need for a parallel port or Altium's USB JTAG Adapter (DT01). To accomplish this, the NanoBoard 3000
Page: NanoBoard 3000 - Host Controller SRAM
Japanese The NanoBoard 3000 includes independent Static RAM for use by the NanoTalk Controller, or more specifically the firmware running within. This is dedicated SRAM that is separate from the independant and common-bus SRAM made available to the User F
Page: NanoBoard 3000 - Host FPGA (NanoTalk Controller)
Japanese The NanoBoard 3000 uses an FPGA device as the controller for the board. This device is commonly referred to as the Host FPGA, or NanoTalk Controller. It is this device into which the 'smarts' of the system – the NanoBoard firmware – gets loaded u
Page: NanoBoard 3000 - Host Status LEDs
The NanoBoard 3000 provides two 1204 size RGB LEDs (S1204RGBSDJC, from Sansen Technology Co., Ltd) – used to reflect the status of the Host Controller FPGA (NanoTalk Controller). Internally, each LED is comprised of three distinct chips – the LEDs of whic
Page: NanoBoard 3000 - Independent SRAM
The NanoBoard 3000 includes independent Static RAM as part of the memory resources available to the on-board User FPGA device, or more specifically a programmed design therein. The term 'independent' is used in this case to distinguish this SRAM – which i
Page: NanoBoard 3000 - Installing Altium Designer
Pre-Installation Checklist Before you begin to install Altium Designer and use your NanoBoard 3000, you will need to do the following: Verify that your system meets the criteria specified at System Requirements Read the End-User License Agreement Check fo
Page: NanoBoard 3000 - IR Receiver
The NanoBoard 3000 provides an IR receiver, courtesy of a TSOP32338 device (from Vishay Semiconductors), for implementation of a remote control system within your FPGA design. The device incorporates an Automatic Gain Control (AGC) circuit using Vishay's
Page: NanoBoard 3000 - MIDI Interface
The NanoBoard 3000 caters for transmission and reception of signals in accordance with the MIDI (Musical Instrument Digital Interface) protocol. The following is a simplified block diagram of the MIDI communications system, with the NanoBoard 3000 as the
Page: NanoBoard 3000 - Motherboard Resources
Related articles: Functional Overview of the NanoBoard 3000, Key Features of the NanoBoard 3000 Each of Altium's 3000-series NanoBoards is a 242 x 176mm (9.5" x 6.9") six layer printed circuit board (4 x signal, 2 x plane), powered by an external 5 Volt r
Page: NanoBoard 3000 - NanoBoard-PC Interface (USB Port)
The NanoBoard 3000 is connected to your PC via one of the computer's standard USB 2.0 ports. The NanoBoard provides a corresponding port through use of a USB B-type connector. USB interface port for connection to a PC. Providing the high-speed interface b
Page: NanoBoard 3000 - Peripheral Board Connector
The NanoBoard 3000 has a single 100-way Female docking connector, for attachment of one single/double size peripheral board. This connector is technically called a 'NANOCONNECT' interface, but more commonly referred to as a peripheral board connector. Per
Page: NanoBoard 3000 - Power
The NanoBoard 3000 is powered by a 5V regulated supply, the power module for which is supplied in the box. If the total power consumption of a given NanoBoard configuration – i.e. with connected expansion devices/peripheral board – exceeds 4A, then a high
Page: NanoBoard 3000 - PS2 Keyboard and Mouse Ports
The NanoBoard 3000 provides two standard PS/2 interfaces, for connection of an IBM PS/2-compatible keyboard and mouse. Each port is implemented using a 6-way mini-DIN (Female) connector and is directly connected to two User FPGA I/O pins, providing CLOCK
Page: NanoBoard 3000 - PWM Power Drivers
The NanoBoard 3000 includes circuitry that allows PWM-driven power control systems to be easily realized. Four I/O pins of the User FPGA are wired to N-channel 'enhancement mode' metal-oxide semiconductor field-effect transistors (NMOSFETs) – catering for
Page: NanoBoard 3000 - Quickstart Guide
NanoBoard3000快速入门手册 Congratulations on purchasing one of Altium's 3000-series NanoBoards. Together with the accompanying Altium Designer software, you are now equipped to discover and explore the world of soft design in a highly-interactive and fun way. U
Page: NanoBoard 3000 - Relays
The NanoBoard 3000 provides four isolated IM relay channels – each channel utilizing an IM03GR, 5V non-latching DPDT relay with one coil (from Tyco Electronics). This device has a maximum switching capacity of 60W, a typical operation time of 1ms (3ms max
Page: NanoBoard 3000 - RGB User LEDs
The NanoBoard 3000 provides a bank of eight 1204 size RGB LEDs (S1204RGBSDJC, from Sansen Technology Co., Ltd). Internally, each LED is comprised of three distinct chips – the LEDs of which provide the component colors Red, Green and Blue. The anode of ea
Page: NanoBoard 3000 - RS-232 Serial Interface
The NanoBoard 3000 provides a PC-style RS-232 serial interface. A DB-9 Male connector is used to provide a serial port, wired as a DCE (Data Communication Equipment), in accordance with the EIA-574 standard. Connection to a host PC (wired as a DTE (Data T
Page: NanoBoard 3000 - RS-485 Serial Interface
The NanoBoard 3000 provides an RS-485 serial interface, catering for high-speed, full duplex differential data transmission. An 8-way PC (modular telephone) jack is used to provide a serial port, connection to which can be achieved using standard twisted-
Page: NanoBoard 3000 - SD Card Reader (Host FPGA)
The Secure Digital (SD) memory card is among a host of such cards available in today's world of storage-hungry devices, such as PDAs and digital cameras. The NanoBoard 3000 provides a reader for this type of memory card – for use by the NanoTalk Controlle
Page: NanoBoard 3000 - SD Card Reader (User FPGA)
The Secure Digital (SD) memory card is among a host of such cards available in today's world of storage-hungry devices, such as PDAs and digital cameras. The NanoBoard 3000 provides a reader for this type of memory card – dedicated for use by the User FPG
Page: NanoBoard 3000 - Serial SPI Flash Memory
The NanoBoard 3000 provides serial Flash memory in the form of two M25P80 8-Mbit devices (from STMicroelectronics). These devices support a serial data rate of 25MHz. The M25P80 is an SPI-compatible device, with both devices accessed through the motherboa
Page: NanoBoard 3000 - SPDIF Interface
The NanoBoard 3000 caters for transmission and reception of digital audio signals in accordance with the S/PDIF (Sony/Philips Digital Interconnect Format) protocol. Signal I/O is handled through two RCA headers. S/PDIF input and output ports. S/PDIF Outpu
Page: NanoBoard 3000 - SPI Real-Time Clock
The current date and time are made available to the NanoTalk Controller through the provision of a low-voltage, SPI Real-Time Clock (RTC) device – a PCF2123, from NXP. The device provides information in terms of: Year, month, day, hours, minutes, and seco
Page: NanoBoard 3000 - System Clocks
The NanoBoard 3000 has an SPI-based system clock generator (an ICS307-02 device) that provides a fixed 20MHz clock and a user-programmable clock providing frequencies from 6 to 200 MHz. Both clocks are made available to the NanoTalk Controller and the Use
Page: NanoBoard 3000 - System JTAG Programming Port
The NanoBoard 3000 provides a dedicated programming port, which is used to load the 'Gold' boot image of the NanoBoard firmware into an associated serial SPI Flash memory device. Programming Port. The 10-pin male header caters for both Hard JTAG (pins 1-4
Page: NanoBoard 3000 - Test-Reset Button
The NanoBoard 3000 provides a push button switch that is wired to an I/O pin of the User FPGA. The button has no intrinsic function – it is simply a switch made available for FPGA design purposes. It is typically used to provide the external reset signal
Page: NanoBoard 3000 - Testing the PC to NanoBoard Connection
Related article: NanoBoard 3000 - Board Communications After connecting your 3000-series NanoBoard to your PC and installing Altium Designer, you should check that the system software can also connect to the NanoBoard. This check is made using the Devices
Page: NanoBoard 3000 - TFT LCD Panel (with Touch Screen)
The NanoBoard 3000 provides high quality color display through a TS8003K TFT (Thin Film Transistor) LCD panel (from Shenzhen Techstar Electronics). The panel also features an analog resistive touch screen. TFT LCD panel with touch screen. From a user pers
Page: NanoBoard 3000 - USB Hub
The NanoBoard 3000 provides a USB 'hub', allowing the connection of up to three USB 2.0-based devices. The three ports are provided courtesy of USB A-type connectors. Three-port USB hub available for connection of USB-based devices. The interface between
Page: NanoBoard 3000 - User DIP-Switch
The NanoBoard 3000 provides an 8-way DIP-switch, with each switch wired to a separate I/O pin of the User FPGA device. This provides you with eight generic switchable signals for use in an FPGA design. Switchable inputs provided courtesy of an 8-way<br>DI
Page: NanoBoard 3000 - User FPGA
The NanoBoard 3000 provides a single FPGA device, to which an FPGA design is targeted and ultimately programmed. Referred to as the 'User FPGA', this device is fixed on the motherboard – there are no daughter boards used with the 3000-series NanoBoards. T
Page: NanoBoard 3000 - User FPGA Power and Program LEDs
The NanoBoard 3000 provides the following two status LEDs associated with the User FPGA: Power LED – this will light (GREEN) when the motherboard's power is switched on. It signifies presence of the 3.3V power supply on the board. Program LED – this will
Page: NanoBoard 3000 - User IO Headers
The NanoBoard 3000 includes two I/O headers that allow user-defined hardware to be interfaced to the User FPGA. These 20-pin headers – designated UH1 and UH2 – cater for a total of 36 User FPGA I/O signals, 18 wired to each. Connect to off-board hardware
Page: NanoBoard 3000 - User Prototyping Area
The NanoBoard 3000 provides a dedicated prototyping area, courtesy of an array of unconnected test points. 36 of these points (around the top edge of the array) are connected directly to I/O pins of the User FPGA – the same I/O pins that are made availabl
Page: NanoBoard 3000 - User USB Port
The NanoBoard 3000 provides a USB 2.0 port for use by a design programmed into the board's User FPGA. The port is provided courtesy of a USB B-type connector. USB 2.0 interface port accessible<br>from an FPGA design. Providing the high-speed interface bet
Page: NanoBoard 3000 - Video Output
The NanoBoard 3000 provides a standard SVGA (Super Video Graphics Array) interface, for connection to any SVGA-compatible monitor. Analog RGB video output (24-bit/80MHz) is made through a DB15F connector. Video output connector. Although the interface is
Page: NanoBoard 3000 - What's in the Box
Figure 1. NanoBoard 3000 package contents. 3000-series NanoBoard with TFT LCD panel and 3V lithium battery affixed Altium Designer software - 12-month Soft Design license Desktop stand - comprising 2 side panels and self-adhesive non-slip feet (flat packe
Page: NanoBoard 3000 Modular Enclosure
Stylish, robust and ready-to-use, the NanoBoard 3000 Modular Enclosure is the perfect solution for deploying the NanoBoard 3000 Smart FPGA Development Board. And its modular design means it's not limited to just one application. Create prototype products,
Page: NanoBoard 3000 Modular Enclosure - Assembly Instructions
The NanoBoard 3000 Modular Enclosure is shipped pre-assembled and ready-to-use. Also included in the box are various components offering optional enclosure configurations depending on the specific application required.       A quick-release key (G) is pro
Page: NanoBoard 3000 Modular Enclosure - Design Collateral
Following are design collateral files necessary to develop and deploy custom hardware: PCB files for Connector Panels and Bridging Panel Wall mount template Decal - Blank Decal - Holes
Page: NanoBoard 3000 Modular Enclosure - What's in the Box
Figure 1. NanoBoard 3000 Modular Enclosure package contents. A - 1 x pre-assembled NanoBoard 3000 Modular Enclosure (includes: blank front panel, 2 x connector panels, 2 x standard end panels) B - 1 x LCD screen front panel (replaces blank panel when LCD
Page: NanoBoard 3000 Series
NanoBoard 3000系列 NanoBoard 3000 シリーズ NanoBoard 3000 NanoBoard 3000 series datasheet NanoBoard 3000XN Schematics NanoBoard 3000AL Schematics NanoBoard 3000XN Reference Design Further information on the NanoBoard 3000 can be found at the dedicated NanoBoard
Page: NanoBoard 3000 SPI System Overview
The NanoBoard 3000 SPI system involves a variety of SPI-compatible slave resources, located across the hardware system – on the motherboard itself and also on certain peripheral boards that plug in to the motherboard. The majority of these SPI resources a
Page: NanoBoard NB2 - Installing Altium Designer
Pre-Installation Checklist Before you begin to install Altium Designer and use your NanoBoard NB2, you will need to do the following: Verify that your system meets the criteria specified at System Requirements Read the End-User License Agreement Check for
Page: NanoBoard NB2 - Quickstart Guide
Congratulations on purchasing an Altium NanoBoard NB2. Together with the accompanying Altium Designer software, you are now equipped to discover and explore the world of soft design in a highly-interactive and fun way. Use the following links to setup you
Page: NanoBoard SPI Communications - Accessing the Common SPI Bus from an FPGA Design
Related articles: NanoBoard SPI Communications - Interface Wiring, Using SPI Flash Memory as Embedded Memory From an FPGA design perspective, the NanoBoard's SPI Controller provides an SPI path from the target FPGA device to each of the common-bus SPI sla
Page: NanoBoard SPI Communications - Interface Wiring
Related articles: NB2DSK01 SPI System Overview, NanoBoard 3000 SPI System Overview Accessing an SPI-compatible resource from within an FPGA design is most easily accomplished by placing and wiring a Serial Peripheral Interface Controller component and an
Page: NanoBoard-NB1
The NanoBoard-NB1 is Altium's legacy development platform for the rapid testing of FPGA designs. It consists of a motherboard with a variety of commonly used peripherals, and a range of plug-in FPGA or CPLD daughter boards.   Altium's latest NanoBoard – t
Page: NanoBoards
Japanese Altium's NanoBoards are unique, reconfigurable hardware platforms that harnesses the power of today's high-capacity, low-cost programmable devices to allow rapid and interactive implementation and debugging of your digital designs. With a NanoBoa
Page: NanoBoards - General Handling Caution
The following cautions and warning apply to use of Altium NanoBoards. This equipment includes exposed electronic components that are highly sensitive to damage from static electricity. Users are cautioned to always follow standard antistatic procedures wh
Page: NanoConnectors
Altium's range of NanoBoards (NanoBoard NB2, 3000-Series NanoBoard) each feature one or more 'NANOCONNECT' interfaces, by which to dock a satellite daughter board or peripheral board(s), where applicable. When a satellite board is plugged-in, such an inte
Page: NanoTalk
The NB2DSK01 includes Altium's proprietary communications protocol, referred to as NanoTalk. This protocol defines and provides a communication path between a PC running Altium Designer and one or more NanoBoards. NanoTalk is implemented as part of the fi
Page: Navigating between Variant Information and the Schematic
Accessing Variant Information from the Schematic You may wish to access the variant-related information for components directly from the schematic. This can be achieved by selecting the components required, right-clicking over one of the components in tha
Page: Navigation in Altium Designer
Altium Designer でのナビゲーション   Navigation To aid navigation of design documents, Altium Designer provides a dedicated Navigation bar (shown below) accessed from within any of the application's document editors. Dedicated document navigation toolbar Alternati
Page: Navigator Panel
Navigator パネル   Function The Navigator panel allows you to browse either the compiled active source document, or all compiled source documents in the active project. The source document(s) can be schematic and/or HDL in nature. The panel utilizes the conn
Page: NB2DSK-SPK01 Resources - Board ID Memory
Board identification is handled courtesy of a DS2406 device (from Dallas Semiconductor). Although the device is actually a dual-addressable switch, it is used for the additional 1kbit of memory that it possesses. Figure 1. 1-Wire memory used<br>to contain
Page: NB2DSK-SPK01 Resources - Docking Connector
The NB2DSK-SPK01 has a 16-way Male connector used to attach it to the NB2DSK01 motherboard, which has a corresponding 16-way Female connector. Figure 1. Docking connector on the NB2DSK-<br>SPK01, used to attach the board to the<br>NB2DSK01 motherboard. Th
Page: NB2DSK-SPK01 Resources - RGB LEDs
The NB2DSK-SPK01 provides six 5mm diameter RGB LEDs (540R2GBC-CA, from HB Electronics). Figure 1. Two of the six RGB LEDs on the NB2DSK-SPK01. Internally, each LED is comprised of three distinct chips – the LEDs of which provide the component colors Super
Page: NB2DSK-SPK01 Resources - Stereo Speakers
Audio output capability on the NB2DSK-SPK01 is provided through the use of two 4Ω speakers. Each speaker has a 60mm body, 50mm cone and delivers 3W output power. Figure 1. One of the speakers used on the NB2DSK-SPK01. Input to these speakers are the diffe
Page: NB2DSK01 - ADC-DAC-I2C
The NB2DSK01 is equipped with general purpose analog-to-digital and digital-to-analog converters, both interfaced to the daughter board FPGA using the I2C bus protocol. Figure 1. ADC/DAC and I2C interface. Analog-to-digital conversion is provided by a 4-c
Page: NB2DSK01 - Board Communications
Communications between the various devices within the system makes extensive use of the technology defined by IEEE Standard 1149.1 – commonly referred to as JTAG. The Desktop NanoBoard NB2DSK01 is connected to your PC using either a USB or parallel connec
Page: NB2DSK01 - Board ID Memory
Board identification is handled courtesy of a DS2406 device (from Maxim). The DS2406 is a 1-Wire compatible device, primarily used to contain a code with which to identify the motherboard. It is also used to contain additional information such as revision
Page: NB2DSK01 - Buzzer Signal
As part of its audio capabilities, the NB2DSK01 provides a hardwired path for a mono-based audio signal from the daughter board FPGA. This signal – a legacy NB1-style Buzzer signal – can be incorporated as input to the NB2DSK01's analog audio mixer.   The
Page: NB2DSK01 - CAN Port
The NB2DSK01 provides a standard CAN (Controller Area Network) interface. The interface provides the ability to send and receive data over a bus conforming to the CAN 2.0B specification. A DB9M connector is used to provide the connection to the external C
Page: NB2DSK01 - Common-Bus Flash Memory
The NB2DSK01 includes Flash memory as part of the common-bus block of memory resources available to the NanoTalk Controller, or more specifically the firmware running within. Figure 1. Common-bus Flash memory used by the<br>NB2DSK01s firmware. The Flash m
Page: NB2DSK01 - Common-Bus SDRAM
The NB2DSK01 includes Synchronous Dynamic RAM as part of the common-bus block of memory resources available to the NanoTalk Controller, or more specifically the firmware running within. Figure 1. Common-bus SDRAM used by the<br>NB2DSK01s firmware. The SDR
Page: NB2DSK01 - Common-Bus SRAM
The NB2DSK01 includes Static RAM as part of the common-bus block of memory resources available to the NanoTalk Controller, or more specifically the firmware running within. Figure 1. Common-bus SRAM used by the<br>NB2DSK01's firmware. The SRAM is provided
Page: NB2DSK01 - Compatability with the NanoBoard-NB1
Altium's Desktop NanoBoard NB2DSK01 has been designed with compatibility – with the NanoBoard-NB1 – in mind. All of the daughter boards available from Altium can be readily used with either the NB2DSK01 or the NB1. Note: With no HDR_L connector, 2-connect
Page: NB2DSK01 - Configuration PROM
The NB2DSK01 uses a Xilinx Platform Flash Configuration PROM device (XCF08PFS48C) in which to store the system's firmware. The firmware gives the NB2DSK01 its 'smarts'. Figure 1. Serial PROM device used to hold the NanoBoard firmware. The XCF08PFS48C is a
Page: NB2DSK01 - Configuring an FPGA Project Automatically
Although an FPGA design project targeting the Desktop NanoBoard NB2DSK01 can be configured manually – by adding a configuration, assigning the required board constraint files and creating a mapping constraint file by hand – the process is greatly simplifi
Page: NB2DSK01 - Daughter Board Test-Reset Button
The NB2DSK01 provides a push button switch that is wired to an I/O pin of the daughter board FPGA. The button has no intrinsic function – it is simply a switch made available for FPGA design purposes. It is typically used to provide the external reset sig
Page: NB2DSK01 - Debug Headers
A total of 16 spare I/O pins on the NanoTalk Controller FPGA are brought out to two 10-pin headers, 8 wired to each (pins 1-8). Pin 9 of each header is tied to ground. Pin 10 is connected to the motherboard's 5V supply, via a 350mA fuse and 3A/40V Schottk
Page: NB2DSK01 - FPGA Daughter Board Connectors
The plug-in daughter boards are mounted onto the NB2DSK01 motherboard using three 100-way Female docking connectors – designated HDR_T1, HDR_L1 and HDR_B1. These are individually referred to as 'NANOCONNECT' interfaces, and collectively as the daughter bo
Page: NB2DSK01 - Generic User Switches
The NB2DSK01 provides a further five push button style switches that are wired to separate I/O pins of both the NanoTalk Controller (Xilinx Spartan-3 FPGA) and the daughter board FPGA. From the NanoTalk Controller's perspective, these switches are used fo
Page: NB2DSK01 - Home-NanoBoard Reset Button
The NB2DSK01 provides a push button switch that is wired to an I/O pin of the NanoTalk Controller FPGA device. The switch is of type SPNO – Single Pole Normally Open. In the open position, it provides a logical High signal to the NanoTalk Controller, chan
Page: NB2DSK01 - Host Status LEDs
The Host status LEDs(labeled 'SL1'..'SL8') are used to indicate the state of the NanoTalk Controller and the various communications links that interface with it, such as Hard JTAG, Soft JTAG and SPI. Figure 1. Host status LEDs. Location on Board The Host
Page: NB2DSK01 - Independent SRAM
The NB2DSK01 also includes independent Static RAM as part of the memory resources available to the NanoTalk Controller, or more specifically the firmware running within. The term 'independent' is used in this case to distinguish this SRAM – which is inter
Page: NB2DSK01 - NanoBoard-PC Interface (Parallel Port)
The NB2DSK01 can be connected to your PC via the computer's standard parallel port. The NB2DSK01 provides a corresponding parallel port through use of a 26-pin Male header. Figure 1. Parallel port interface for connection to PC. When you launch Altium Des
Page: NB2DSK01 - NanoBoard-PC Interface (USB Port)
The NB2DSK01 can be connected to your PC via one of the computer's standard USB 2.0 ports. The NB2DSK01 provides a corresponding port through use of a USB B-type connector. Figure 1. USB interface port for<br>connection to a PC. Providing the high-speed i
Page: NB2DSK01 - NanoTalk Controller
The NB2DSK01 uses a Xilinx Spartan-3 device (XC3S1500-4FG676C) as the controller for the board. This device is commonly referred to as the NanoTalk Controller. It is this device into which the 'smarts' of the system – the NanoBoard firmware – gets loaded
Page: NB2DSK01 - NanoTalk Master-Slave Headers
To allow multiple NanoBoards to be connected in a daisy-chain configuration, two 10-pin headers are provided – designated HDR4 ('NANOTALK IN') and HDR5 ('NANOTALK OUT'). Figure 1. NanoTalk Master and Slave connectors, used for daisy-chaining NanoBoards. T
Page: NB2DSK01 - Peripheral Board Connectors
The plug-in peripheral boards are each mounted onto the NB2DSK01 motherboard using a single 100-way Female docking connector. Provision is made for the connection of up to three such boards, with the corresponding connectors labeled 'PERIPHERAL BOARD A',
Page: NB2DSK01 - Power
The NB2DSK01 is powered by a 5V regulated supply, the power module for which is supplied in the box. If the total power consumption of a given NanoBoard configuration – i.e. daisy-chained and/or with connected expansion devices/user boards – exceeds 4A, t
Page: NB2DSK01 - PS2 Mouse and Keyboard Ports
The NB2DSK01 provides two standard PS/2 interfaces, for connection of an IBM PS/2-compatible mouse and keyboard. Each port is implemented using a 6-way mini-DIN (Female) connector and is directly connected to two daughter board FPGA I/O pins, providing CL
Page: NB2DSK01 - RS-232 Serial Port
The NB2DSK01 provides a PC-style RS-232 serial interface. A DB-9 Male connector is used to provide a serial port, wired as a DCE (Data Communication Equipment), in accordance with the EIA-574 standard. Connection to a host PC (wired as a DTE (Data Termina
Page: NB2DSK01 - SD Card Reader
The Secure Digital (SD) memory card is among a host of such cards available in today's world of storage-hungry devices, such as PDAs and digital cameras. The NB2DSK01 provides a reader for this type of memory card, by way of a DM1B-DSF-PEJ connector (HRS6
Page: NB2DSK01 - Serial SPI Flash Memory
The NB2DSK01 provides serial Flash memory in the form of two M25P80 8-Mbit devices (from STMicroelectronics). These devices support a serial data rate of 25MHz. The M25P80 is an SPI-compatible device, with both devices accessed through the NB2DSK01's SPI
Page: NB2DSK01 - SPI Real-Time Clock
The current date and time are made available to the NanoTalk Controller through the provision of a low-voltage, SPI Real-Time Clock (RTC) device – a DS1391U-33, from Maxim. The device provides information in terms of: Year, month, day, hours, minutes, and
Page: NB2DSK01 - Stereo Audio
The NB2DSK01 provides a powerful stereo audio system, complete with analog mixer, power amplifier and various sound output methods. The following sections take a closer look at the various stages involved in the implementation of this system. Sound Input
Page: NB2DSK01 - System Clocks
The NB2DSK01 has an SPI-based system clock generator (an ICS307-02 device) that provides a fixed 20MHz clock and a user-programmable clock providing frequencies from 6 to 200 MHz. Both clocks are made available to the NanoTalk Controller (Xilinx Spartan-3
Page: NB2DSK01 - System JTAG Programming Port
The NB2DSK01 provides a dedicated host programming port, which is used to load updated NanoBoard firmware directly into the Xilinx Platform Flash Configuration PROM. Figure 1. Update firmware using the<br>dedicated Host Programming Port. The 10-pin male h
Page: NB2DSK01 - TFT LCD Panel (with Touch Screen)
The NB2DSK01 provides high quality color display through a Hitachi TX09D50VM1CAA TFT (Thin Film Transistor) LCD panel. The panel also features an analog resistive touch screen. Figure 1. TFT LCD panel with touch screen. From a user perspective, you can ei
Page: NB2DSK01 - User Board Headers
The NB2DSK01 includes two JTAG extender headersfor connection of user boards, such as third party development boards or production prototype boards. These 10-pin headers – designated HDR1 and HDR2 – facilitate the inclusion of user boards into the Hard an
Page: NB2DSK01 - User DIP-Switch
The NB2DSK01 provides an 8-way DIP-switch, with each switch wired to a separate I/O pin of the daughter board FPGA device. This provides you with eight generic switchable signals for use in an FPGA design. Figure 1. Switchable inputs provided courtesy<br>
Page: NB2DSK01 - User IO Headers
The NB2DSK01 includes two I/O headers that allow user-defined hardware to be interfaced to the daughter board FPGA. These 20-pin headers – designated UH1 and UH2 – cater for a total of 36 daughter board FPGA I/O signals, 18 wired to each. Figure 1. Connec
Page: NB2DSK01 - User LEDs
The NB2DSK01 provides a bank of eight Green LEDs, labeled 'USER LEDS'. Each LED is wired to, and driven from, a separate I/O pin of the daughter board FPGA device. The LEDs provide a visual output for signals in an FPGA design. Figure 1. Visual output thr
Page: NB2DSK01 - What's in the Box
Figure 1. NanoBoard NB2 package contents. NanoBoard NB2 including stand, TFT LCD panel, Stereo Speaker Assembly, 3V lithium battery and 3 x peripheral boards Daughter board (packaged separately, not shown) Altium Designer software - 12-month Soft Design l
Page: NB2DSK01 Auto-Configuration - Configuring the Project
Prior to using the auto-configuration feature, ensure the following: The daughter board carrying the FPGA device to which the design is targeted is plugged into the NB2DSK01 motherboard. Any peripheral boards carrying resources used by the FPGA design are
Page: NB2DSK01 Auto-Configuration - Identifying System Hardware
Before taking a closer look at the auto-configuration procedure itself, it is a good idea to understand the technology by which such automatic configuration of the system is made possible. The key to being able to configure an FPGA design project automati
Page: NB2DSK01 Constraint System Overview
The constraint system in place for the Desktop NanoBoard NB2DSK01 utilizes various constraint files covering: Resources and pin-mapping local to the NB2DSK01 motherboard and satellite peripheral and daughter boards Connection of a satellite board (periphe
Page: NB2DSK01 Motherboard Resources
Altium's Desktop NanoBoard NB2DSK01 is a 300 x 165mm (11.8" x 6.5") eight layer printed circuit board (6 x signal, 2 x plane), powered by an external 5 Volt regulated supply. One of the plane layers is associated exclusively to GND. The other plane layer
Page: NB2DSK01 SPI System Overview
The NB2DSK01 SPI system involves a variety of SPI-compatible slave resources, located across the hardware system – on the NB2DSK01 motherboard itself and also on certain peripheral boards that plug in to the motherboard. These SPI resources are accessible
Page: NC Drill Output Options
NC Drill File output is configured in the NC Drill Setup dialog. The NC Drill Setup Dialog The NC Drill Setup dialog provides you with tools to completely configure your NC Drill file output options. The NC Drill Format region of the dialog allows you to
Page: NEC Infrared Transmission Protocol
The NEC IR transmission protocol uses pulse distance encoding of the message bits. Each pulse burst (mark – RC transmitter ON) is 562.5µs in length, at a carrier frequency of 38kHz (26.3µs). Logical bits are transmitted as follows: Logical '0' – a 562.5µs
Page: Net Antennae
Creating Design Rules Design Rules Rule Category: Manufacturing Description This rule operates at a net level in the design to flag any track or arc end that is not connected to any other primitive and thus forms an antenna. The specified value is the set
Page: Netlist Outputs
The Netlist Outputs category of the OutputJob Editor allows you to create the following Output Generators: Cadnetix Calay EDIF for PCB EESof Intergraph Mentor BoardStation MultiWire OrCad/PCB2 PADS Pcad for PCB PCAD PCADnlt Protel2 Protel Racal RINF SciCa
Page: Netlisters
Page: Nets to Ignore
Description Defines which nets should be ignored during autoplacement with the Cluster Placer. Constraints None Rule Classification Unary How Duplicate Rule Contentions are Resolved Contentions are not possible. Rule Application During autoplacement with
Page: New Configurable Generic FPGA Logic Components
The Summer 09 release of Altium Designer sees the addition of two new components to the FPGA Configurable Generic integrated library (FPGA Configurable Generic.IntLib) - a clock manager (CLOCK_MANAGER) and a pulse width modulator (PWM). CLOCK_MANAGER The
Page: New Features in Altium Designer 10
Altium Designer 10 新功能介绍 Altium Designer 10 の新機能 Altium Designer mini-site AltiumLive Complete list of Altium Designer updates Departing from seasonally-themed release naming and instead utilizing a streamlined, no-fuss numbering format, the latest releas
Page: New Features in the Summer 09 Release of Altium Designer
Altium Designer Summer09新特性 Neue Funktionen in der Altium Designer Summer 09 Release Altium Designer Summer 09 の新機能 Discover what's new in Altium Designer The Summer 09 release of Altium Designer continues the process of keeping you plugged into a continu
Page: New Features in the Winter 09 release of Altium Designer
Discover what's new in Altium Designer There is a better way The Winter 09 release of Altium Designer brings significant new and enhanced features to unify the design process, helping you create a real return on your innovation. It's the next phase in our
Page: New FPGA Peripheral Core Components
The Summer 09 release of Altium Designer sees the inclusion of three new FPGA peripheral core components. A configurable Wishbone 1-Wire Master Controller (WB_OWM_V2), and a configurable LED Controller – in both Wishbone (WB_LED_CTRL) and non-Wishbone (LE
Page: New Literature
Almost all the literature available for Altium Designer has been updated for Altium Designer 6.0. All documents can be easily accessed through Altium Designer’s Knowledge Center (accessed by pressing F1 in the software) and are also available in the Help
Page: New Rule - Hole to Hole Clearance
It also ensures manufacturing compatibility of stacked microvias. When enabled, it will flag any multiple vias / pads at the same location or overlapping pad / via holes. There is also a flag to allow stacked microvias or not (as shown below). Technical R
Page: New Rule - Minimum Solder Mask Sliver
Minimum Solder Mask Sliver helps identify narrow sections of solder mask that may cause manufacturing problems later. Ensuring that there is a minimum width of solder mask across the board, this rule checks the distance between any two solder mask opening
Page: New Rule - Net Antennae
Previously only available in the CAM editor the new Net Antennae rule in PCB allows you to identify any errors before generating any manufacturing output. Figure 1. The Net Antennae rule setup page Figure 2. A violation correctly identified in the editor
Page: New Rule - Silk Over Component Pads
Silk Over Component Pads, a new rule added to the Manufacturing Rule set, ensures correct clearance between silk screen and copper in component pads that is exposed through openings in the solder mask. This check ensures that the distance is greater or eq
Page: New Rule - Silk to Silk Clearance
The legibility of silk layers will be ensured with new Silk to Silk Clearance rule, a new rule added to the Manufacturing Rule set. Silk to Silk Clearance checks the clearance between any silkscreen text and other silkscreen primitives. The check ensures
Page: New Separator for Schematic Designator Suffix
回路図デジグネータ サフィックスの新しいセパレータ   Each part in a multi-part schematic component is uniquely identified by an alpha or numeric suffix. Altium Designer 13.2 extends the numeric suffix support by adding the choice of a dot or a colon as the suffix separator.    Fo
Page: Nios II Data Organization
Data organization refers to the ordering of the data during transfers. There are two general types of ordering: BIG ENDIAN – the most significant portion of an operand is stored at the lower address LITTLE ENDIAN – the most significant portion of an opera
Page: Nios II Memory Space
The Nios II uses 32-bit address buses providing a 4GByte linear address space. All memory access is in 32-bit words, which creates a physical address bus of 30-bits. The processor's address space is broken into four main areas (three usable and one reserv
Page: Nios II Pin Description
The pinout of the Nios II has not been fixed to any specific device I/O – allowing flexibility with user application. The Nios II contains only unidirectional pins (inputs or outputs).   The following pin description is for the processor when used on the
Page: Non-Wishbone Components
Catering for designs that typically feature older, 8- or 12-bit processors, Altium Designer provides a range of peripheral components to extend the functionality of your chosen processor and/or enable communication with, and control over, devices external

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Page: Obstacle Avoidance During Drag Operations
Interactive routing has been improved to better utilize the Ignore, Walk-around, and Push and Hug commands during drag operations. The dragging command has been improved to leverage the power of the interactive router. Dragged tracks and vias are able to
Page: ODB Output Options
ODB++ output options are configured in the ODB++ Setup dialog. The ODB Setup Dialog The ODB++ Setup dialog displays layer stackups for embedded board arrays (panelization). Notice here that any compatibility violations display in red. The ODB++ Setup dial
Page: Offset Holes in Pads
It is now possible to offset the pad land patterns from the hole. An example of a pad with offset hole
Page: OpenBus Arbiter Component
Figure 1. The OpenBus<br>Arbiter component. The Arbiter component provides a simple means of sharing a slave peripheral device between multiple masters within the OpenBus System. Typically, it is used where two or more devices require access to shared phy
Page: OpenBus Component Placement
Placement of OpenBus components is simply a case of clicking the required entry in the OpenBus Palette panel, positioning at the desired location in the workspace, and clicking again to effect placement. Familiar schematic placement controls, such as flip
Page: OpenBus Interconnect Component
Figure 1. The OpenBus<br>Interconnect component. The Interconnect component provides a means of accessing one or more peripheral devices over a single OpenBus interface. It connects directly to the IO or MEM ports of a processor component, facilitating co
Page: OpenBus System - Configuring Arbiter Components
Configuration of an Arbiter component is performed using the Configure OpenBus Arbiter dialog (Figure 1). Figure 1. Configuring an Arbiter component. In comparison to its schematic counterpart – WB_MULTIMASTER – configuration of the Arbiter is greatly str
Page: OpenBus System - Configuring Clock, Reset and Interrupt Lines
Management of the clock, reset and interrupt lines for the system are handled in the OpenBus Signal Manager dialog – accessed by clicking on the button on the OpenBus toolbar (or using the Tools » OpenBus Signal Manager command). These signals are handled
Page: OpenBus System - Configuring Interconnect Components
Configuration of an Interconnect component is performed using the Configure OpenBus Interconnect dialog (Figure 1). Figure 1. Configuring an Interconnect component. If you are familiar with configuration of the WB_INTERCON component in the schematic world
Page: OpenBus System - Configuring Processor Memory and Peripherals
An OpenBus System incorporating a 32-bit processor will typically involve the connection of slave memory and peripheral devices – to the processor's MEM and IO ports respectively. Unlike schematic-based design however, you are not required to manually def
Page: OpenBus System - Port Addition & Removal
When you initially place Interconnect and Arbiter components they will have a default number of ports: Interconnect – one master port (m0) and one slave port (s0) Arbiter – one master port (m0) and two slave ports (s0 and s1). Hover the cursor over a port
Page: OpenBus System - Rearranging Ports
You may find, during the course of wiring up the OpenBus components, that certain ports could be better placed to ease wiring and make the system more readable. The OpenBus Editor provides the ability to change the location of a port (or ports) around a c
Page: OpenBus System - Reshaping Links
The shape of an OpenBus Link can be modified after placement – either manually, or by using one of the various link-related commands available on the OpenBus toolbar. Manually Changing Link Shape Clicking on an OpenBus Link after placement will display on
Page: OpenBus System Building Blocks
The starting point for any OpenBus System document is the placement of the required devices that will consitute your system. In the schematic world, design components reside in libraries and are placed on the sheet directly from the Libraries panel. In th
Page: OpenBus System Design - Basics
At the heart of the OpenBus System is the OpenBus System document. This document is created and managed using Altium Designer's OpenBus Editor (Figure 1). Figure 1. The OpenBus Editor. The OpenBus Editor becomes active when the active document in the main
Page: OpenBus Tutorial - Configuring Processors, Peripherals and Memory
In our OpenBus System, we have three components that fall under this category of configuration: TSK3000A processor (designated MCU) Parallel Port Unit (designated GPIO) SRAM Controller (designated XRAM). Let's configure these components now. Double-click
Page: OpenBus Tutorial - Configuring the Arbiter Components
Configuration of an Arbiter component in the OpenBus System is also a more streamlined process, in relation to its schematic-based counterpart, WB_MULTIMASTER. The system again handles much of the configuration for you, so information such as data and add
Page: OpenBus Tutorial - Configuring the Clocks, Resets and Interrupts
Management of the clock, reset and interrupt lines for the system are handled in the OpenBus Signal Manager dialog (Tools » OpenBus Signal Manager). These lines are handled separately from the main bus link between devices, to simplify the bus. We shall u
Page: OpenBus Tutorial - Configuring the Interconnect Components
Configuration of an Interconnect component in the OpenBus System is a far more streamlined process in comparison to its schematic-based counterpart, WB_INTERCON. The system handles much of the configuration 'behind the scenes' as it were, so information s
Page: OpenBus Tutorial - Configuring the Processor Address Space
In the OpenBus System we have built, we have connected slave memory and peripheral devices to the processor's MEM and IO ports respectively. Unlike schematic-based design however, we are not required to manually define the mapping of these devices into th
Page: OpenBus Tutorial - Configuring the System
Now we have built the OpenBus System, it is time to configure it. The following is a list of areas that generally need to be configured for any OpenBus System: Processors, peripherals and memories Interconnect components Arbiter components Clock, Reset an
Page: OpenBus Tutorial - Creating the OpenBus System
Now we have the FPGA project set up, we can concentrate on building the OpenBus System. Before we do, we should identify just what exactly it is that we want to describe using the OpenBus System document. If you open the schematic document DSF_Mandelbrot.
Page: OpenBus Tutorial - Initial Project Preparation
As we are converting an existing design, it is a good idea to have that design open. We will need to jump to it for reference – ensuring that we keep the new OpenBus System design true to the configuration of the original. Navigate to, and open, the exist
Page: OpenBus Tutorial - Interfacing to the Top-Level Schematic
With the OpenBus System defined, we now need to interface the OpenBus System document with our top-level schematic. This, as has been mentioned previously, is handled through a sheet symbol placed on the schematic sheet. The sheet entries required to popu
Page: OpenBus Tutorial - Linking System Components
We have placed the required devices for the system, now it's time to wire them all together. In the OpenBus System, two components are connected to each other using a single link, referred to as an OpenBus link. Links are made between ports of devices, wi
Page: OpenBus Tutorial - Placing Components into the System
The starting point for any OpenBus System document is the placement of the required devices that will consitute the system. These OpenBus components, as they are called, are placed from the OpenBus Palette panel. Open this panel from the menu associated w
Page: Opening Internet links in an External Web Browser
外部の Web ブラウザでインターネットリンクを開く   There are many areas within Altium Designer where clicking on a link will result in the display of internet-based content. Altium Designer provides the ability to view this content either directly inside the Altium Designer en
Page: Operating the Counter Module
Once the design has been processed and downloaded into the physical FPGA device, the instrument can be used. Displays and controls for the instrument can be found on the device's associated instrument panel. This panel enables you to effectively use the i
Page: Operating the Crosspoint Switch Module
Once the Crosspoint Switch module has been configured and the design processed and downloaded into the physical FPGA device, the instrument can be used. Displays and controls for the instrument can be found on the device's associated instrument panel. Thi
Page: Operating the Digital IO Module
Once the Digital I/O Module has been configured and the design processed and downloaded into the physical FPGA device, the instrument can be used. Displays and controls for the instrument can be found on the device's associated instrument panel. This pane
Page: Operating the Frequency Generator Module
Once the design has been processed and downloaded into the physical FPGA device, the instrument can be used. Displays and controls for the instrument can be found on the device's associated instrument panel. This panel enables you to effectively use the i
Page: Operating the Logic Analyzer
The host computer is connected to the target Logic Analyzer instrument using the IEEE 1149.1 (JTAG) standard interface. This is the physical interface, providing connection to physical pins of the FPGA device in which the instrument has been embedded. The
Page: Organization of the Software Platform
Introduction to the Software Platform   Organization of the Software Platform   Using the Software Platform Builder   Glossary   The Software Platform consists of device stacks and software services. This section describes both parts and how they are rela
Page: Orthographic Projection
Want see the difference between Orthographic and Perspective projection? Here it is ... Left: This image displays the design in Perspective Projection Right: This image displays the design in Orthographic Projection With Perspective Projection the mode ac
Page: Other Hardware
Japanese The following is a list of additional hardware devices manufactured by Altium as part of, or in relation to, its Innovation Station. USB JTAG Adapter Desktop Stereo Speaker Assembly NB2DSK-SPK01 NanoConnectors
Page: Outline Vertices Editor for Polygonal Pours and Regions
ポリゴンとリジョンの外形頂点エディタ   Outline Vertices Editor for Polygon Pours and Regions Offering additional versatility when defining polygonal-based objects in a design – Polygon Pours and Regions (solid, polygon pour cutout, board cutout) – Altium Designer provides
Page: Output Generators for Altium Designer 2004
Output Generators Altium Designer As well as the standard output generators (such as netlisters and BOMs) included with Altium Designer 2004, additional outputers can be added at any time. This page includes all additional outputers that are currently ava
Page: Output Generators for Altium Designer 6
Output Generators Altium Designer As well as the standard output generators (such as netlisters and BOMs) included with Altium Designer 6, additional outputers can be added at any time. This page includes all additional outputers that are currently availa
Page: Output Generators for DXP 2002
Output Generators DXP (2002 Release) As well as the standard output generators (such as netlisters and BOMs) included with Protel DXP, additional outputters can be added at any time. This page includes all additional outputters that are currently availabl
Page: Output Panel
Function The Output panel provides detailed information with respect to all stages of the Process Flow when compiling, synthesizing, building and ultimately downloading the chosen FPGA design to the physical device. The information displayed in the panel
Page: Overshoot- Falling Edge
Description Specifies the maximum allowable overshoot (ringing below the base value) on the falling edge of the signal. Constraints Maximum (Volts) the value for the maximum permissible overshoot on the falling edge of the signal. (Default = 1.000). Rule
Page: Overshoot- Rising Edge
Description Specifies the maximum allowable overshoot (ringing above the top value) on the rising edge of the signal. Constraints Maximum (Volts) the value for the maximum permissible overshoot on the rising edge of the signal. (Default = 1.000). Rule Cla

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Page: P-CAD Libraries
P-CAD 2006 P-CAD 2006 Libraries (536 MB) This download includes the entire set of P-CAD 2006 libraries (which are the same set of libraries delivered with P-CAD 2004). These are documented in the Library Index Spreadsheet (4.8 MB). Note: You will need to
Page: P-CAD to Altium Designer Terminology Guide
This is a high-level roadmap to guide you in understanding how P-CAD terminology translates and can be found in Altium Designer. High-level points of interest or difference are noted where appropriate. Resources for additional reading in the Altium Design
Page: Pad
Japanese Description A pad is a primitive design object. It is used to create an interconnection point from a component pin to the routing on the board. Pads can be used individually as free pads in a design or, more typically, they are used in the PCB Li
Page: Panel Shortcuts
パネルのショートカット Common Panel Shortcuts HOME Jump to first entry in panel END Jump to last entry in panel ↑ Move to previous entry in the panel ↓ Move to next entry in the panel ← Collapse expanded top-level entry or sub-folder → Expand collapsed top-level ent
Page: Parallel Segment
Description Specifies the distance two track segments can run in parallel, for a given separation. Constraints Layer Checking specifies where the two track segments to be checked should reside: Same Layer (default) - the track segments for the targeted ne
Page: Part Catalog and Part Choices
Part Catalog と Part Choice   Supply Chain Insight and Part Choices As a board designer, you capture the idea for that next great product using a collection of logically wired components across a number of schematic sheets. The components you use will have
Page: Passing PCB Pin Swap Data to the Linked FPGA Project
After running the automatic Optimizer and/or interactive pin swapping tools, you will need to propagate the resulting changes on the PCB document through to the linked FPGA project. The first step in doing this is to update the schematic sheet(s) in the P
Page: Paste Mask Expansion
The shape that is created on the paste mask layer at each pad site is the pad shape, expanded or contracted radially by the amount specified by this rule. Constraints Expansion the value applied to the initial pad shape to obtain the final shape on the pa
Page: Patching Instructions for AD10 Update 13
The latest release of Altium Designer includes a patching system to improve the update process. The patching system dramatically reduces the size of the downloads required to install an update. To install this update as before you can simply click on the
Page: PB01 Audio-Video Peripheral Board
Altium's Audio / Video peripheral board PB01 provides a Stereo Audio CODEC and a host of video capabilities, available for use by the FPGA device resident on the currently attached daughter board. The PB01 has the following features: 24-bit Stereo Audio C
Page: PB01 Resources - Audio
The PB01's audio capabilities are provided by a CS4270 24-bit, 192kHz stereo audio CODEC (from Cirrus Logic). The CODEC caters for both analog and digital audio I/O. Figure 1. CS4270 Stereo Audio CODEC<br>device. Device Power and Reset Power for the digit
Page: PB01 Resources - Video Input Capture
The PB01 supports the connection of external NTSC or PAL analog video signals. Both Composite Video and S-Video inputs are supported: Connection of a Composite Video signal is made through two RCA phono jacks, designated J5 and J6, which cater for the Lum
Page: PB01 Resources - Video Output
The PB01 supports the output of analog video signals in three formats – VGA, Composite Video and S-Video: Analog RGB (VGA) video output is made through a DB15F connector, designated J1.   Figure 1. VGA output connector.   Composite Video output is made th
Page: PB02 Mass Storage Peripheral Board
Altium's Mass Storage peripheral board PB02 provides a host of Memory Card/ATA Interface resources, available for use by the FPGA device resident on the currently attached daughter board. The PB02 has the following features: Secure Digital (SD) memory car
Page: PB02 Resources - ATA and IDE Interfaces
The ATA (Advanced Technology Attachment) bus interface – commonly referred to as the IDE (Integrated Drive Electronics) bus interface – is a standard interface used for connection of storage devices, such as hard disk drives, to a processor in a computer.
Page: PB02 Resources - CF Card Reader
The PB02 provides a reader for Type 1 Compact Flash (CF) memory cards. The Compact Flash interface is smaller than, but electrically identical to, the PCMCIA-ATA interface. Figure 1. Compact Flash (CF) memory card reader. The -ATA SEL input (pin 9) has be
Page: PB02 Resources - SD Card Reader
The Secure Digital (SD) memory card is among a host of such cards available in today's world of storage-hungry devices, such as PDAs and digital cameras. The PB02 provides a reader for this type of memory card, by way of a DM1B-DSF-PEJ connector (HRS60900
Page: PB03 Resources - Ethernet Port
The PB03 provides a fast Ethernet connection, supporting 100Base-TX and 10Base-T, for operational speeds of up to 100Mbps and 10Mbps respectively. An 8P8C ('RJ45') modular connector is used to provide the Ethernet port. Connection to the external network
Page: PB03 Resources - IrDA Interface
The PB03 provides a fast infrared transceiver, courtesy of a TFDU6102 device (from Vishay Semiconductors). This device is compliant with the IrDA® (Infrared Data Association) standard for fast infrared data communications (FIR), and can also be used for r
Page: PB03 Resources - USB Port
The PB03 provides a USB 2.0 port, identical to that found on the NB2DSK01 motherboard. The port is provided courtesy of a USB B-type connector. Figure 1. USB 2.0 interface port. Providing the high-speed interface between a processor in an FPGA design and
Page: PB03 USB - IrDA - Ethernet Peripheral Board
Altium's USB - IrDA - Ethernet peripheral board PB03 provides a host of communications resources, available for use by the FPGA device resident on the currently attached daughter board. The PB03 has the following features: 10/100 Fast Ethernet interface U
Page: PB30 Prototyping Peripheral Board
Datasheet Board Schematics Parent article: Peripheral Boards Altium's Prototyping peripheral board (PB30) provides a rapid prototyping space to quickly test out additional hardware resources – accessible by the User FPGA device on a NanoBoard NB2 or 3000-
Page: PC to NanoBoard Communications
The NanoBoard is an integral part of Altium's LiveDesign-enabled design system and forms a sophisticated reconfigurable platform for design implementation and debug. The system makes extensive use of the JTAG and Nexus standards to provide flexible and ex
Page: PCB 3D Movie Management and Configuration
3D PCB Movie Editor Parent article: PCB 3D Video A PCB 3D Video is generated from a sequence of key frames – snapshots of your board that, when published in a video format, result in a smoothly interpolated movie that can be used to highlight and showcase
Page: PCB 3D Orthographic Projection
More precise object geometry can now be achieved through new PCB 3D Orthographic Projection. Exact positioning of components and details that may be hidden from views are some of the perspectives that are now possible, providing an even more realistic vie
Page: PCB 3D Video
Japanese http://wiki.altium.com/pages/viewpage.action?pageId=25071621 3D PCB 'flyovers' If a picture can 'tell a thousand words', it stands to reason that a series of pictures could convey far more information – a sequence of images used to visually educa
Page: PCB API Constants
AllLayers AllLayers = [MinLayer..eConnectLayer]; AllObjects AllObjects = [FirstObjectId..LastObjectId]; AllPrimitives AllPrimitives = [ eArcObject , eViaObject , eTrackObject , eTextObject , eFillObject , ePadObject , eComponentObject , eNetObject , ePoly
Page: PCB API Design Objects Interfaces
A PCB design object on a PCB document is represented by its interface. An interface represents an existing object in memory and its properties and methods can be invoked. A PCB design object is basically a primitive or a group object. A primitive can be a
Page: PCB API Functions
The major PCB Functions are defined and implemented in the RT_PCBProcs unit. Unit conversion functions Function RealToMils (C : TReal) : TReal; Function RealToMMs (C : TReal) : TReal; Function CoordToMils (C : TCoord) : TReal; Function CoordToMMs (C : TCo
Page: PCB API System Interfaces
This section covers the PCB API System Object Interfaces. System Object Interfaces IPCB_ServerInterface interface PCB API System Interfaces IPCB_Sheet interface IPCB_Library interface Layer Object Interfaces IPCB_LayerStack interface IPCB_LayerObject inte
Page: PCB API Types
The enumerated types are used for many of the PCB object interfaces methods which are covered in this section. For example the IPCB_Board interface has a LayerIsUsed [L : TLayer] : Boolean property. You can use this Enumerated Types section below to check
Page: PCB Design View
PCB Design View   A modern PCB can be compact, dense and small in size, making it difficult to present important design information in the documentation. To help in this process the PCB Editor supports placing a specific view of a PCB design within the wo
Page: PCB Editor
Japanese The PCB Editor allows you to create, edit and verify the PCB design, as well as generate the output files required to manufacture the printed circuit board. This comprehensive reference provides information on the editing capabilities of the PCB
Page: PCB Export - Ansoft Neutral File
PCB 导出 – Ansoft中间文件 Japanese Ansoft design and develop software tools for engineers for electromagnetics design, and circuit and system simulation. The Ansoft DesignerSI platform integrates EM analysis with circuit and system simulation in a highly accura
Page: PCB Filter Panel
Function The PCB Filter panel allows you to construct filters through the creation of logical queries. A defined filter can then be applied to the active PCB document, allowing you to select and edit multiple objects with great accuracy and efficiency. Co
Page: PCB Inspector Panel
Function The PCB Inspector panel enables you to interrogate and edit the properties of one or more design objects in the active PCB document. Used in conjunction with appropriate filtering, the panel can be used to make changes to multiple objects of the
Page: PCB Library Panel
Function The PCB Library panel enables you to browse component footprints stored in the active PCB library document and edit their properties. The panel also offers the ability to pass on any changes made to them directly to the PCB design document. Conte
Page: PCB List Panel
Function The PCB List panel allows you to display design objects from the active document in tabular format, enabling you to quickly inspect and modify object attributes. When used in conjunction with the PCB Filter panel, it enables you to display just t
Page: PCB Object and Layer Transparency
PCB オブジェクトとレイヤの透過表示    PCB Object and Layer Transparency Settings Offering increased control over the display of objects within the design workspace, Altium Designer provides support for setting the transparency of each object type individually, and on a
Page: PCB Panel
Function The PCB panel allows you to browse the current PCB design using various filter modes to determine which object types or design elements are listed, highlighted or selected. It also has editing modes for certain object types or design elements tha
Page: PCB Printout Output Options
Altium Designer's job output options support print-based output for both two-dimensional and three-dimensional PCB representations. With 2D print output, complete control of the printout is possible; you can include/exclude based on layer, and within each
Page: PCB Processes
This section covers the PCB processes and their parameters (if any). Table of PCB processes AdvancedRoute process AlignComponents process Annotate process ApertureLibrary process ArrangeComponents process AutopositionComponentTexts process AutoRoute proce
Page: PCB Project Configurations
Japanese PCB Configuration Manager Parent article: Production Release PCB design projects (*.PrjPcb) are design-side entities, containing the source documents that collectively define the object being designed. They represent the design team's intent on h
Page: PCB Query Functions
This section covers PCB Query functions used by the Query System in Altium Designer. All Object Type Check Description Returns objects on the PCB document. Syntax All : Boolean Examples All All = True Returns all objects. Not All All = False Returns no ob
Page: PCB Release View
PCB Release 画面   Parent article: Vault-Driven Electronics Design An example of the <b>PCB Release</b> view. The PCB Release view (View»PCB Release View) is the graphical interface to Altium Designer's PCB Process Manager – used to perform the board design
Page: PCB Routing
PCB 配線 After component placement, the most important stage of the PCB design process is routing the connections. Altium Designer includes a number of intuitive interactive routing features to help you efficiently and accurately route your board, from a si
Page: PCB-Specctra Interface Improvements
The Summer 09 release of Altium Designer sees enhancements to the Specctra exporter. The exporter has been updated to offer translation of specifically formatted width and clearance design rules, enabling a smoother transition and greater success when usi
Page: PCBLib Filter Panel
Function The PCBLIB Filter panel allows you to construct filters through the creation of logical queries. A defined filter can then be applied to the active PCB component footprint, or all component footprints in the active PCB library, allowing you to se
Page: PCBLib Inspector Panel
Function The PCBLIB Inspector panel enables you to interrogate and edit the properties of one or more design objects in the active PCB component footprint (or all component footprints in the active PCB library). Used in conjunction with appropriate filter
Page: PCBLIB List Panel
Function The PCBLIB List panel allows you to display design objects associated with one or more PCB component footprints in tabular format, enabling you to quickly inspect and/or modify object attributes. When used in conjunction with the PCBLIB Filter pa
Page: Performance and Efficiency Upgrade to PCB Graphics System
PCB Performance Improvements A significant effort has been put into re-engineering the DirectX graphics engine for PCB environment in the Altium Designer Winter 09 release. This has resulted in greatly improved performance with lower memory overhead and e
Page: Performance comparison of graphics cards
Printable version Video cards are a critical hardware element that can have a large impact on both the performance and stability of systems. These benchmarks help you choose the right 3D PCB graphics engine for your needs and budget. Choose the right hard
Page: Performance Improvements (AD10)
Japanese Performance Enhancements - Plane Refresh Altium Designer 10 delivers a range of performance improvements, when compared to the previous Summer 09 release. Areas benefiting from improved performance include: Workspace and Project opening and closi
Page: Performing Pin Swapping on the PCB
Having defined the Pin Groups as appropriate and enabled pin swapping for the required components, the actual process of swapping pins can now be performed. With the PCB document active, pin swapping tools are available from the Tools » Pin/Part Swapping
Page: Performing Signal Integrity Analyses
This tutorial looks at performing Signal Integrity (SI) analyses. It covers setting up design parameters like design rules and Signal Integrity models, starting up Signal Integrity from the Schematic and PCB Editors, configuring the tests to be used in th
Page: Peripheral Board 1-Wire Communications
The NB2DSK01 provides a 1-Wire® serial bus (ONE_WIRE_DB_PB), which is connected from its daughter board connector through to each of its peripheral board connectors. This provides the ability to communicate directly from a processor in an FPGA design, wit
Page: Peripheral Board Common Services
In addition to IO pins, each peripheral board connector on the NB2DSK01 motherboard provides pins for the following common services: JTAG Signals Both Hard and Soft JTAG signals are wired to the peripheral board connectors, in the same way as for the user
Page: Peripheral Board ID Memory
Board identification is handled courtesy of a DS2406 device (from Dallas Semiconductor). Although the device is actually a dual-addressable switch, it is used for the additional 1kbit of memory that it possesses. Figure 1. Example 1-Wire memory<br>device
Page: Peripheral Boards
With the NanoBoard NB2, or 3000-series NanoBoard, peripheral resources can be made available to the target (user) FPGA through the use of removable peripheral boards, providing a simple and cost-effective method for rapid prototyping of your hardware conc
Page: Permitted Layers
Description Specifies which layers components can be placed on during placement with the Cluster Placer. Constraints | Permitted Layers | - | the layers permitted to be used by the Cluster Placer during autoplacement. The following layer options are avail
Page: Philips RC5 Infrared Transmission Protocol
The Philips RC5 IR transmission protocol uses Manchester encoding of the message bits. Each pulse burst (mark – RC transmitter ON) is 889us in length, at a carrier frequency of 36kHz (27.7us). Logical bits are transmitted as follows: Logical '0' – an 889u
Page: Physical Device Pin State Panel
The Pin State Panel shows the configuration of every pin, and can also show the current pin activity. Function The pin states panel associated with a physical FPGA device provides information concerning the mapping of interface ports in the source FPGA de
Page: Pick and Place Output Options
Pick and Place output options are configured in the Pick and Place Setup dialog. The Pick and Place Setup Dialog The Pick and Place Setup dialog provides you with tools to completely configure your pick and place output options. Use the Pick and Place Set
Page: Pin, Differential Pair and Sub-Part Swapping
How do I use FPGA Pin Swapping during PCB layout? Working in harmony with Altium Designer's interactive routing and BGA escape routing capabilities is the pin, pair and part swapping system. This feature provides all the benefits of traditional pin-swappi
Page: Place Dashed Line Script
Using the Place Dashed Line script The place dashed line script makes it easy to added lines as a dashed pattern in the PCB editor. Download Version 0.1.1 PlaceDashedLine_V011.zip Notes The generated pattern can be customized within the script. The tracks
Page: Place or Reposition Components from the PCB Panel
It is now possible to place or reposition components directly from the PCB Panel. To use this feature select one or more components in the panel and the either choose Reposition Components from the right click menu or simply drag the components into the P
Page: Place Rectangle Script
The place rectangle script makes the task of adding four tracks aligned as a rectangle easier in the PCB editor. Download Version 0.95 PlaceRectangle95.zip Installation The following step will add a new entry into the Place menu in the PCB editor so that
Page: Place Spiral track
Place Spiral Track The spiral track script was attached to a thread on the old Altium Designer forum. Because the forum moved to a new platform the original link you could find here is not longer valid. Check the new forum at live.altium.com for informati
Page: Placement Rules
Component Orientations Height Nets to Ignore Permitted Layers Room Definition Component Clearance
Page: Placing a Counter Module
The FRQCNT2 device enables the accurate frequency measurement of periodic signals in a design. Figure 1 shows an example of how the FRQCNT2 device is wired into a design. Figure 1. Using the FRQCNT2 Frequency Counter in a design. In the example circuit ab
Page: Placing a Crosspoint Switch Module
The configurable Crosspoint Switch module provides an efficient means by which to switch signals in a design. Figure 1 shows a simple example circuit using this instrument.   The circuitry in Figure 1 has been constructed to simplify illustration of how t
Page: Placing a Custom Instrument
Placement can be made directly from the Libraries panel. With the library active, simply click on the entry for the component and then click on the Place CUSTOM_INSTRUMENT button. Alternatively, click and drag an instance of the instrument directly onto t
Page: Placing a Digital IO Module
The configurable Digital I/O Module provides an efficient and uncomplicated means by which to monitor/generate digital signals in a design. Figure 1 shows a simple example of how the device is wired into an FPGA design. Figure 1. Using a Digital I/O modul
Page: Placing a Frequency Generator Module
The CLKGEN device provides a simple method for generating a signal of desired frequency in a design. Figure 1 shows an example of how the CLKGEN device is wired into a design. Figure 2. Using the CLKGEN Frequency Generator in a design. In the example circ
Page: Placing an Arbiter Component
As with all OpenBus components, the Arbiter component resides on, and is placed from, the OpenBus Palette panel. Simply click on the entry for the component, in the Connectors region of the panel. The component will appear floating on the cursor ready for
Page: Placing an Interconnect Component
As with all OpenBus components, the Interconnect component resides on, and is placed from, the OpenBus Palette panel. Simply click on the entry for the component, in the Connectors region of the panel. The component will appear floating on the cursor read
Page: Placing the Logic Analyzer
The configurable LAX instrument provides an efficient means of analyzing the logical levels of signals in a design. The figure below shows a simple example of how the device is wired into a design. Using a LAX instrument to analyze signals in a design. In
Page: Plane Rules
Power Plane Connect Style Power Plane Clearance Polygon Connect Style
Page: Plug-n-Play Software Platform Builder
Altium Designer Winter 09 introduces a new feature suite: the Software Platform Builder. This intuitive editor allows you to easily assemble a Software Platform for your hardware. The Software Platform is a layer of software assembled in the Software Plat
Page: Point Transactions in AltiumLive
AltiumLive のポイントの取り扱い Punkty AltiumLive   Parent article: AltiumLive All active users on an Organization's account with Altium have equal access to its central 'pool' of AltiumLive Points, for use within the AltiumLive community (for example when voting f
Page: Polygon Connect Style
Description Specifies the style of the connection from a component pin to a polygon plane. Constraints Connect Style   Defines the style of the connection from a pin of a component, targeted by the scope (Full Query) of the rule, to a polygon plane. The f
Page: Polygon Pour
Description A polygon pour is a group design object. It creates a solid, hatch-filled (lattice) or outline-only area on the selected PCB layer. Also referred to as copper pours, they are similar to area fills, except that they can fill irregularly shaped
Page: Polygon Pours and Copper Regions
A common requirement on a printed circuit board is large areas of copper. It could be a hatched region of grounding copper on an analog design; a large, solid region of copper for carrying heavy power supply currents; or a solid ground area for EMC shield
Page: Power Monitoring Functionality at the Hardware-Level
Before looking at how the power monitoring functionality is accessed within the software, it is worth taking a look at the underlying hardware, by which such power monitoring of the system is made possible. On the NB2DSK01 motherboard, current monitoring
Page: Power Monitoring on the Desktop NanoBoard NB2DSK01
As the number of daughter boards and peripheral boards continues to grow – both those designed by Altium and those made externally – the number of different hardware configurations possible for a Desktop NanoBoard NB2DSK01 becomes considerable. Add to thi
Page: Power Plane Clearance
Description Specifies the radial clearance created around vias and pads that pass through but are not connected to a power plane. Constraints Clearance the value for the radial clearance. (Default = 20mil). Rule Classification Unary How Duplicate Rule Con
Page: Power Plane Connect Style
Description Specifies the style of the connection from a component pin to a power plane. Constraints Connect Style defines the style of the connection from a pin of a component, targeted by the scope (Full Query) of the rule, to a power plane. The followi
Page: Powerful new Interactive Routing features
Interactive Routing Improvements Interactive routing is the single most time-consuming activity for board designers. The Winter 09 release includes a range of enhancements to increase the user experience and productivity in this area. Interactive Differen
Page: PPC405A Data Organization
Data organization refers to the ordering of the data during transfers. There are two general types of ordering: BIG ENDIAN – the most significant portion of an operand is stored at the lower address LITTLE ENDIAN – the most significant portion of an opera
Page: PPC405A Interrupts
The 32 external interrupt input signals that can be wired to the wrapper's Peripheral I/O Interface are not connected internally. The two level-sensitive interrupts (critical and non-critical) provided by the immersed PPC405 core are therefore not current
Page: PPC405A Memory Space
The PPC405A uses 32-bit address buses providing a 4GByte linear address space. All memory access is in 32-bit words, which creates a physical address bus of 30-bits. Memory space is broken into three main areas, as illustrated in Figure 1. Figure 1. Memor
Page: PPC405A Pin Description
The pinout of the PPC405A has not been fixed to any specific device I/O – allowing flexibility with user application. The PPC405A contains only unidirectional pins (inputs or outputs).   The following pin description is for the processor when used on the
Page: Predefined Views for PCB in 3D
事前に定義した視点で PCB を 3D 表示   Displaying your board in 3D is the closest thing to having the real board in your hands, and all before sending it for a prototyping spin. However the beauty of having the physical board in your hands, is that you can naturally tu
Page: Preparing the Board for Design Transfer
Chinese Japanese This tutorial shows how to define the board shape, configure the drawing sheet, setup the layers, and define any keepout requirements, in preparation for transferring the design from the schematic editor. In this tutorial, we will look at
Page: Private Server Licenses - Configuring Usage
Licencje typu Private Server - konfiguracja użycia licencji   Main article: Using a Private Server License Once a Private Server license has been added to a Private License Server, it is typically configured with respect to its usage – which users, or def
Page: Private Server Licenses - Examining Usage
Licencje typu Private Server - sprawdzanie użycia   Main article: Using a Private Server License Having installed your Private License Server, activated/added the required Private Server licenses and configured how those licenses are to be used, it is onl
Page: Processor Debug Panel
Function The debug panel available for an OCD-version MCU provides access to that processor's internal registers and memory spaces, as well as providing a disassembled view of the embedded software running within. Content and Use The panel is essentially
Page: Processor-based FPGA Design
Japanese Developing the Application How do I Decide which Processor to use? How do I add Peripherals and IO to my Processor? How do I Access Wishbone Peripherals in Software? How do I Navigate around my Source Code? How do I Reformat the Appearance of my
Page: Production Release
量産リリース   High-Integrity Board Design Release Management A Walk Through...the Board Design Release Process Parent article: Vault-Driven Electronics Design Getting deep and dirty 'under the bonnet' of a design truly is an Engineer's playground. The fun of c
Page: Profiling
Related article: Tutorial - Using Profiling Information to Improve Locate Options When writing the embedded source code to run on a target processor within a design, the 'holy grail' is to implement the required algorithms as efficiently and as optimizabl
Page: Programming a Xilinx Configuration Device on the Production Board
During design development, the NanoBoardprovides the ability to bootstrap the FPGA devicelocated on the currently inserted Daughter Board, at power-up. Program download to the FPGA is carried out using dedicated Serial Flash RAM. When the design is moved
Page: Programming In-System Flash Memory for a Xilinx Spartan-3AN Device
The Xilinx® Spartan™-3AN family of FPGAs feature In-System Flash (ISF) memory. To a design programmed into and running on such a device, this memory is presented as SPI-based serial Flash memory – similar to the dedicated SPI Flash memory found on an Alti
Page: Project Compiler Error Reference
This comprehensive reference describes each of the possible electrical and drafting violations that can exist in source documents when compiling a project. The process of compiling is integral to producing a valid netlist for a project. Connectivity aware
Page: Project Document Previews
Project Document プレビュー   Parent article: Home Page You are no doubt aware of Altium Designer's support for graphically previewing single design documents, or all design documents in a particular project – with the ability to open a document in the design
Page: Project Management
中文 Japanese What is an Altium Designer Project? The starting point for every design created in Altium Designer is a project. An Altium Designer project is a set of design documents whose output defines a single implementation. For example, the schematics
Page: Project Navigation
Working between the schematic and the PCB is an essential part of the board design process. Altium Designer includes dedicated features and tools to help with the navigation process, including: Cross Probe - click on a component / pin / net in one editor,
Page: Project Options
Project settings are configured in the Options for Project dialog. You can access this from the Projects menu on the main menubar, or by right-clicking on the project name in the Projects panel. The options available to you include: Compiler error check s
Page: Project Shortcuts
Project のショートカット C, C Compile the current design project C, R Recompile the current design project C, D Compile Document C, O Open the Options for Project dialog for the current project CTRL + ALT + O Access the Open Project Documents dialog for the curre
Page: Projects Panel
Figure 1. Three related projects open in the Projects panel. Function The Projects panel displays all projects that are currently open, along with their constituent documents contained therein. Any open documents that have not been created as part of a pr
Page: Protel 3 SP1 Installation notes
Service Pack Information Installation Notes To install the Service Pack run the downloaded file and follow the instructions. Compatible with both the licensed and trial versions of Protel Version 3. The Service Pack modifies the existing Protel Version 3
Page: Protel 3 SP1 Installation notes0
Service Pack Information Installation Notes To install the Service Pack run the downloaded file and follow the instructions. Compatible with both the licensed and trial versions of Protel Version 3. The Service Pack modifies the existing Protel Version 3
Page: Protel 99 Installation Notes
Protel 99 SE Service Pack 6 Information Installation Notes To install the Service Pack run the downloaded file and follow the instructions. Compatible with both the licensed and trial versions of Protel 99 SE, but not suitable for Protel 99. The Service P
Page: Providing Hardware Acceleration
Altium Designer's ASP peripheral component is essentially used as a 'container' for C source functions that are implemented in hardware through use of the CHC technology. The ASP peripheral enables a host processor to access and 'communicate' with the har
Page: PS2 Commands
The following sections detail common commands that can be sent from a host processor to a connected PS/2 keyboard or mouse, and vice-versa. Commands Sent from a Host Processor Table 1 and Table 2 list some of the common commands that can be sent from a ho
Page: PS2 Keyboard Scan Codes
When a key on the keyboard is pressed, a code is sent to the host CPU. With the aid of ASCII look-up tables, the host can determine the function of the pressed key. The transmitted code is called a scan code and is further sub-classed as a 'make' code in
Page: PS2_W - Accessible Internal Registers
All Wishbone communication is carried out through two dedicated registers – the Wishbone Control register (WCREG) and Wishbone Data register (WDREG) respectively. Wishbone Control Register (WCREG) Address: 0h Access: Read and Write Value after Reset: 00h
Page: PS2_W - Block Diagram
Figure 1 shows a high-level block diagram for the PS2_W component. Figure 1. PS2_W block diagram. For information on the internal registers for the PS2_W that can be accessed from the host processor, see Accessible Internal Registers.
Page: PS2_W - Host to Controller Communications
Communications between a 32-bit host processor and the PS2_W are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible internal
Page: PS2_W - Operational Overview
The PS2_W Controller provides the Wishbone interface between a processor (host) on the one side and a PS/2 device (keyboard or mouse) on the other. The host processor sends data to and receives data from the PS2_W Controller, through the Controller's inte
Page: PS2_W - Pin Description
The following pin description is for the PS2_W when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be made
Page: PS2_W - Transmission Protocols
The PS2_W Controller implements a bidirectional protocol for synchronous serial transmission between the host and the PS/2 device (keyboard or mouse). The PS/2 device sends information to the Controller, for example when a key is pressed on the keyboard,
Page: PS2_W - Wishbone PS2 Controller
Figure 1. PS2_W - Wishbone PS2 Controller. The PS/2 Controller component (PS2_W) provides a bidirectional, synchronous serial interface between a host processor and a PS/2 device (keyboard or mouse).   Supply of these soft cores under the terms and condit
Page: Publish to PDF
Publish to PDF allows you to publish PDF documents from the OutputJob Editor. Any number of outputs including Schematic, OpenBus, PCB, PCB3D, BOM and Assembly Drawings can be collated into PDFs using the Output Generators in the Output Job Editor. Figure
Page: Publishing Destinations
Japanese Publishing Destinations offer you the ability to publish release data for an Item Revision (Blank Board and Assembled Board Items only) directly from an Altium Vault or Output Job to a storage space, such as Box.net, Amazon S3, an FTP server, or
Page: Putting Signal Integrity in its Place
This article describes what is required to address possible signal integrity issues that may arise in a design. In the past, tracks on a circuit board could be effectively considered as simple connections. Newer logic families and faster clock speeds have

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Page: Query Language Reference
What is a Query? Underlying Altium Designer is a powerful data filtering and editing system that lets you instruct the software to return you a specified set of objects. This instruction is entered in the form of a Query. A query is a string you enter usi
Page: Query Operators
This section covers Query Operators from the Query Helper dialog in Altium Designer. Arithmetic Operators Addition Operator + Example: NetPinCount + NetViaCount Subtraction Operator, - Example: ArcStopAngle - ArcStartAngle Multiplication operator, * Examp
Page: QuickGuide - Migrating to an Altium Vault
This QuickGuide outlines the procedural steps to quickly migrate your existing library components – stored in standalone symbol and model libraries, Integrated Libraries or Database Libraries – across to an Altium Vault. This document assumes a level of u
Page: QuickGuide - Upgrading to Version 1.1 of the Altium Vault Server
Related article: Altium Vault Server - Centralized Supply Chain Management The following changes have been implemented in version 1.1 of the Altium Vault Server: For access security reasons, the default data location has changed from \Users\<ProfileName>\

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Page: Radial Diameter Dimension
Angular Dimension Baseline Dimension Center Dimension Datum Dimension Leader Dimension Linear Dimension Linear Diameter Dimension Radial Dimension Standard Dimension Description A radial diameter dimension is a group design object. It allows for the dimen
Page: Radial Dimension
Angular Dimension Baseline Dimension Center Dimension Datum Dimension Leader Dimension Linear Dimension Linear Diameter Dimension Radial Diameter Dimension Standard Dimension Description A radial dimension is a group design object. It allows for the dimen
Page: Re-targeting the design to the Production Board
Chinese Once the design has been captured, the first thing you will want to do is to see if it can be synthesized and if a place and route can be performed. What is required to target a design to your board? The design captured in the source documents (sc
Page: Real Time Manufacturing Rule Checking
Realtime CAM Checks New rules have been added at the PCB layout stage to improve overall system productivity. A range of constraints can now be checked in real-time during the design process and before the fabrication of files, helping you avoid unnecessa
Page: Region
Description A region is a primitive, polygon-type object that can be placed on any layer. It can be configured to be positive (placed as a copper region) or negative (placed as a polygon pour cutout) or be multi-layer (placed as a board cutout). When usin
Page: Release Info
Altium Designer 6.9 web update Altium continues to deliver electronics design tools that break the mould, with the latest release – Altium Designer 6.9. Altium Designer 6.9 takes Altium Designer 6.8 one step further, building on market-leading features su
Page: Release Information on Generated Outputs
Japanese When generating documentation for a PCB project, there needs to be some way of indicating which Item and revision the documentation relates to, as well as the configuration of the design project used in the release, and any applicable driving var
Page: Release Manager
The design release process needs to be tightly managed in order to control the design source data at release time, and after the release. This feature helps to control source data at release time and beyond by providing a clear vision of projects history,
Page: Release Manager - How To
Define where releases are to be stored Go in DXP>Preferences, Release Management tab. Define here where you want the release files to be stored. If 'Store all releases in repository' is not checked, the releases for any given project will be stored under
Page: Release Manager concepts
The Release Manager helps control the design data source and its outputs at release time and through time by taking a snapshot of the design source and generating the outputs from it. The working environment During the design phase, engineers work from a
Page: Release notes for Altium Designer
Altium Designer のリリースノート Complete list of Altium Designer 2013 updates What's New in Altium Designer Use the following links to access release notes pertinent to each of the versions that have been released for Altium Designer 2013. Version 13.3 (13 Jun 2
Page: Release notes for Altium Designer 10 (Platform Build 10.391.22084)
Altium Designer 10 (Platform Build 10.391.22084) のリリースノート Additional Resources Complete list of Altium Designer updates Date: 24 February 2011 Releae notes for: Release notes for Altium Designer 10 (Platform Build 10.391.22084) Release notes for Altium De
Page: Release notes for Altium Designer 10 update (10.467.22184)
Japanese Additional Resources Complete list of Altium Designer updates Updated plug-ins from release 10.391.22084 to 10.467.22184 Date: 24 March 2011 Note: The Platform Build number remains at 10.391.22084 for this release, as the Altium Designer Base mod
Page: Release notes for Altium Designer 10 update (10.494.22274)
Japanese Additional Resources Complete list of Altium Designer updates Updated plug-ins from release 10.467.22184 to 10.494.22274 Date: 12 April 2011   System Components: Altium Designer Base 3037 The full component update option can be set to maintain pa
Page: Release notes for Altium Designer 10 update (10.516.22330)
Japanese Additional Resources Complete list of Altium Designer updates Updated plug-ins from release 10.494.22274 to 10.516.22330 Date: 29 April 2011   System Components: Altium Designer System 1997 An Access Violation that used to happen when switching b
Page: Release notes for Altium Designer 10 update (10.537.22385)
Japanese Additional Resources Complete list of Altium Designer updates Updated plug-ins from release 10.516.22330 to 10.537.22385 Date: 13 May 2011 Note: Installation of the below modules will bring their revision up to 10.537.22385. Note: The Platform Bu
Page: Release notes for Altium Designer 10 update (10.545.22410)
Japanese Additional Resources Complete list of Altium Designer updates Updated plug-ins from release 10.537.22385 to 10.545.22410 Date: 19 May 2011 System Components: Altium Designer Base 4616 Now UNC paths will be able to be used when generating ODB++ ou
Page: Release notes for Altium Designer 10 update (10.554.22457)
Japanese Additional Resources Complete list of Altium Designer updates Updated plug-ins from release 10.545.22410 to 10.554.22457 Date: 26 May 2011 System Components: Altium Designer Base 4886 Column widths are now restored correctly in the browse for com
Page: Release notes for Altium Designer 10 update (10.564.22479)
Japanese Additional Resources Complete list of Altium Designer updates Updated plug-ins from release 10.554.22457 to 10.564.22479 Date: 1 June 2011 System Components: Altium Designer Base 4383 The Configuration Memory tab, part of the Options for Embedded
Page: Release notes for Altium Designer 10 update (10.577.22514)
Japanese Additional Resources Complete list of Altium Designer updates Updated plug-ins from release 10.564.22479 to 10.577.22514 Date: 14 June 2011 System Components: Altium Designer Base 2532 Cutouts no longer generated on mechanical and drill layers in
Page: Release notes for Altium Designer 10 update (10.589.22577)
Japanese Additional Resources Complete list of Altium Designer updates Updated plug-ins from release 10.577.22514 to 10.589.22577 Date: 12 July 2011 System Components: Altium Designer Base 3171 The files now open within the library project for svndblib. V
Page: Release notes for Altium Designer 10 update (10.600.22648)
Japanese Additional Resources Complete list of Altium Designer updates Updated plug-ins from release 10.589.22577 to 10.600.22648 Date: 28 July 2011 Note: The Platform Build number remains at 10.589.22577 for this release, as the Altium Designer Base modu
Page: Release notes for Altium Designer 10 update (10.651.22821)
Japanese Additional Resources Complete list of Altium Designer updates Updated plug-ins from release 10.600.22648 to 10.651.22821 Date: 15 September 2011   System Components: Altium Designer Base 5294 Display the license Subscription Status and date. Syst
Page: Release notes for Altium Designer 10 update (10.700.22943)
Japanese Additional Resources Complete list of Altium Designer updates Updated plug-ins from release 10.651.22821 to 10.700.22943 Date: 10 October 2011   System Components: Altium Designer Base 4530 No ERC Directives in schematic have been enhanced and ca
Page: Release notes for Altium Designer 10 update (10.747.23074)
Japanese Additional Resources Complete list of Altium Designer updates Updated plug-ins from release 10.700.22943 to 10.747.23074 Date: 10 November 2011   System Components: Altium Designer Base 5489 Floating Net Label violations are no longer raised for
Page: Release notes for Altium Designer 10 update (10.771.23139)
Japanese Additional Resources Complete list of Altium Designer updates Updated plug-ins from release 10.747.23074 to 10.771.23139 Date: 23 November 2011   System Components: Altium Designer Base 5177 Improved performance of "Find Partial Matches" stage of
Page: Release notes for Altium Designer 10 update (10.818.23272)
Japanese Additional Resources Complete list of Altium Designer updates Update 15: Updated plug-ins from release 10.771.23139 to 10.818.23272 Date: 19 December 2011 Key highlights Custom pad shapes As a result of the very first BugCrunch report that was vo
Page: Release notes for Altium Designer 10 update (10.890.23450)
Altium Designer 10 (10.890.23450) のリリースノート Complete list of Altium Designer updates Update 16: Updated plug-ins from release 10.818.23272 to 10.890.23450 Date: 6 February 2012 Key highlights Improvement to impedance and width calculations This release del
Page: Release notes for Altium Designer 10 update (10.972.23595)
Altium Designer 10 (10.972.23595) のリリースノート Complete list of Altium Designer updates Update 17: Updated plug-ins from release 10.890.23450 to 10.972.23595 Date: 21 March 2012 Key highlights Via Stitching Of particular importance for RF and High Speed desig
Page: Release notes for Altium Designer 10/12
Altium Designer 10/12 のリリースノート Complete list of Altium Designer updates Use the following links to access release notes pertinent to each of the updates that have been released for Altium Designer. Release notes for Altium Designer Update 24 (10.1377.2700
Page: Release notes for Altium Designer Update 18 (10.1051.23878)
Altium Designer 更新 18 (10.1051.23878) のリリースノート Complete list of Altium Designer updates Update 18: Updated plug-ins from release 10.972.23595 to 10.1051.23878 Date: 27 April 2012 Key highlights STEP model preview  A visual preview is now available when se
Page: Release notes for Altium Designer Update 19 (10.1089.24016)
Altium Designer 更新 19 (10.1089.24016) のリリースノート Complete list of Altium Designer updates Update 19: Updated plug-ins from release 10.1051.23878 to 10.1089.24016 Date: 23 May 2012 Key highlights SubVersion 1.7 Support  Support for the latest version of Subv
Page: Release notes for Altium Designer Update 20 (10.1133.24352)
Altium Designer 更新 20 (10.1133.24352) のリリースノート Complete list of Altium Designer updates Update 20: Updated plug-ins from release 10.1089.24016 to 10.1133.24352 Date: 21 June 2012 Key highlights New PCB connection drawing options  New options have been imp
Page: Release notes for Altium Designer Update 21 (10.1181.24817)
Altium Designer 更新 21 (10.1181.24817) のリリースノート Complete list of Altium Designer updates Update 21: Updated plug-ins from release 10.1133.24352 to 10.1181.24817 Date: 24 July 2012 Key highlights Improvements to Re-Annotate Re-annotate has been improved and
Page: Release notes for Altium Designer Update 22 (10.1271.26245)
Altium Designer 更新 22 (10.1271.26245) のリリースノート Complete list of Altium Designer updates Update 22: Updated plug-ins from release 10.1181.24817 to 10.1271.26245 Date: 19 October 2012 Key highlights Incremental Unroute We have included a new feature in PCB
Page: Release notes for Altium Designer Update 23 (10.1327.26514)
Altium Designer 更新 23 (10.1327.26514) のリリースノート Complete list of Altium Designer updates Update 23: Updated plug-ins from release 10.1271.26245 to 10.1327.26514 Date: 23 November 2012 Key highlights New deselect touching line and rectangle commands The PCB
Page: Release notes for Altium Designer Update 24 (10.1377.27009)
Altium Designer 更新 24 (10.1377.27009) のリリースノート Complete list of Altium Designer updates Update 24: Updated plug-ins from release 10.1327.26514 to 10.1377.27009 Date: 18 December 2012  Key highlights Support for Cortex-M3 Discrete Processors NXP LPC1000 se
Page: Release notes for Altium Designer Version 13.0
Altium Designer 13.0 のリリースノート  Complete list of Altium Designer 2013 updates Version 13.0 Date: 01 February 2013 Key highlights Project document previews. A new Workspace View (View>>Workspace) has been added showing a graphical preview of all the documen
Page: Release notes for Altium Designer Version 13.1
Altium Designer バージョン 13.1 のリリースノート Complete list of Altium Designer 2013 updates Version 13.1 Date: 28 February 2013 This update brings improvements to a number of areas affecting stability and performance. The Altium Installer has also been greatly impr
Page: Release notes for Altium Designer Version 13.2
Altium Designer バージョン 13.2 のリリースノート Complete list of Altium Designer 2013 updates Version 13.2 Date: 10 May 2013 Key highlights The following is a list of key new features and enhancements, delivered in this latest update. Core Technologies ActiveBOM Acti
Page: Release notes for Altium Designer Version 13.3
Altium Designer バージョン 13.3 のリリースノート Complete list of Altium Designer 2013 updates  Key highlights The following is a list of key new features and enhancements, delivered in this latest update. ActiveBOM Enhancements ActiveBOM enhancements including curren
Page: Release notes for NanoBoard Firmware update (1.0.26)
Applicable: NanoBoard 3000XN Update from: 1.0.15 to 1.0.26 Applicable: Nanooard 3000AL Update from: 1.0.17 to 1.0.26 Clock settings are correctly saved on change. Issues caused by Windows computer coming out of sleep mode with NB3000 connected have been r
Page: Release Notes for the Summer 09 release of Altium Designer
Summer 09 Build 9.0.0.17654 (from Build 8.3.0.16776) PCB A crash that occurred when the PCB print settings were configured in an outjob when no PcbDoc was open has been fixed. The "Copy Room Formats" command will copy all the objects within or touching a
Page: Release Notes for the Summer 09 Service Pack 1 Release of Altium Designer
Summer 09 Service Pack 1 Build 9.1.0.18363 (from Build 9.0.0.17654) PCB Significantly improved Libraries panel performance when browsing PCB libraries with a lot of STEP models. Fixed problem that prevented PCB documents being opened under Windows 2000 op
Page: Release Notes for the Summer 09 Service Pack 2 Release of Altium Designer
Summer 09 Service Pack 2 Build 9.2.0.18802 (from Build 9.1.0.18363) PCB After Undoing a component footprint change (following Component Properties), Undo successfully replaced the footprint, but some manipulation was required to re-enable display of the c
Page: Release Notes for the Summer 09 Service Pack 3 HotFix 1 Release of Altium Designer
Summer 09 Service Pack 3 HotFix 1 Build 9.3.1.19182 (from Build 9.3.0.19150) System-level The dialog for saving multiple documents that appears during the Exit of Altium Designer now saves files correctly. Release Notes for the Summer 09 release of Altium
Page: Release Notes for the Summer 09 Service Pack 3 Release of Altium Designer
Summer 09 Service Pack 3 Build 9.3.0.19150 (from Build 9.2.0.18802) FPGA Support for Xilinx Virtex-6 devices has been added. Support for Xilinx Spartan-3A, Spartan-3ADSP and Spartan-3E Automotive devices has been added. The DataWidth property of the Custo
Page: Release Notes for the Summer 09 Service Pack 4 Release of Altium Designer
Summer 09 Service Pack 4 Build 9.4.0.20159 (from Build 9.3.1.19182) FPGA and Embedded Actel Libero 9.0 is now supported. Xilinx ISE 12.1 is now supported. Some stability issues with the TSK3000 processor while using interrupts heavily or in multithreaded
Page: Release Notes for the Winter 09 release of Altium Designer
Winter 09 Build 8.0.0.15895 (from Build 7.1.0.14670) PCB The DRC options for split planes are now correctly saved with the PCB document. 3D bodies that are part of a component now respect the Locked and Locked Primitive properties of the component. Fixed
Page: Release Notes for the Winter 09 Service Pack 1 Release of Altium Designer
Winter 09 Service Pack 1 Build 8.1.0.16385 (from Build 8.0.0.15895) PCB The Layer Name is no longer truncated in Pad properties dialog. Now the board outline edge and sheet outline edge will be drawn using the current configuration's "Board Line Color" an
Page: Release Notes for the Winter 09 Service Pack 2 Release of Altium Designer
Winter 09 Service Pack 2 Build 8.2.0.16457 (from Build 8.1.0.16385) PCB The excessive CPU usage on idle systems with open PCB documents and DirectX enabled has been resolved. Components containing STEP models now flip correctly. FPGA The auto connect sign
Page: Release Notes for the Winter 09 Service Pack 3 Release of Altium Designer
Winter 09 Service Pack 3 Build 8.3.0.16776 (from Build 8.2.0.16457) PCB Fixed excessive CPU usage in DirectX mode when moving the cursor but nothing on the screen was redrawing. Fixed the issue causing certain Quadro cards to reboot after repouring a poly
Page: Report Outputs
How do I create a Bill of Materials (BOM)? The Report Outputs category of the OutputJob Editor allows you to create the following Output Generators: Bill of Materials Component Cross Reference Report Project Hierarchy Simple BOM Report Single Pin Nets Con
Page: Reports and Netlist Generation
Publish to PDF Generating a Custom Bill of Materials Netlisters Smart PDF
Page: RISC Processor Background
RISC, or Reduced Instruction Set Computer, is a term that is conventionally used to describe a type of microprocessor architecture that employs a small but highly-optimized set of instructions, rather than the large set of more specialized instructions of
Page: Room
Description A room is a primitive design object. It is a region that assists in the placement of components. Rectangular or polygon-type rooms can be placed on either the top or bottom layer of the board and can either be placed empty - associating compon
Page: Room Definition
This rule specifies a rectangular region where components are either allowed in, or not allowed in. Constraints Room Locked allows you to lock the room in its current position within the design, preventing accidental movement either manually or by the Aut
Page: Routing - Differential Pair Routing
Chinese A differential signaling system is one where a signal is transmitted down a pair of tightly coupled carriers, one of these carrying the signal, the other carrying an equal but opposite image of the signal. Differential signaling was developed to c
Page: Routing Corners
Specifies the corner style to be used during autorouting. Constraints Style specifies which routing corner style to use. The following three styles are available: 90 Degrees * 45 Degrees (default) * Rounded | Setback these two fields allow you to define a
Page: Routing Layers
Specifies which layers are allowed to be used for routing. Untill AD10 SP14 the rule was just for the Autorouter Constraints Each of the signal layers currently defined for the design - as defined by the layer stackup - are listed. By default, the Allow R
Page: Routing Priority
Assigns a routing priority to the net(s) targeted by the rule. The Autorouter uses the assigned priority value to gauge the routing importance of each net in the design and hence determine which nets should be routed first. Constraints Routing Priority th
Page: Routing Rules
Routing ルール Width Routing Via Style Routing Topology Routing Priority Routing Layers Routing Corners Fanout Control Differential Pair Routing
Page: Routing Topology
The topology of a net is the arrangement or pattern of the pin-to-pin connections. By default, pin-to-pin connections of each net are arranged to give the shortest overall connection length. A topology is applied to a net for a variety of reasons; for hig
Page: Routing Via Style
Specifies the routing via diameter and hole size. Constraints Via Diameter specifies constraint range values to be adhered to with respect to the diameters of vias placed when routing the board. The following individual values are definable: Minimum - the
Page: Running your Output Media
To run your selected Output Medium, first select the required Output Medium and then you can either: Click on the button at the top of the Output Media column. It becomes active and displays your selected Output Media name and the appropriate icon when yo

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Page: Sandbox
Test, edit, 2011 Nov 18 Here is my first post to Altium's new Wiki site. Let see what a bunch of members can do. I think first off for me will be the FAQ area. Enjoy     This is a frequently asked question This is a frequently asked answer This is a frequ
Page: Saving Variant Definitions
Your Variant Definitions are saved in your project. You can also save your variant defintions into an ASCII test file. For both regions of the Assembly Variant Management dialog you can save the entire grid contents, or specifically selected data, into an
Page: Scanning the Chains
Commands are provided for testing the Hard and Soft Devices JTAG chains directly, both of which are available from the Tools menu when a Devices view is active in the main design window. Note: Both commands are only available when the Devices view is conf
Page: Schematic Annotation based on Part Location
Part の位置に基づいた回路図アノテーション   Altium Designer's schematic annotation feature is unquestionably powerful. But its reliance on the component designator as the sole reference for component location when processing annotation order can lead to unexpected designat
Page: Schematic API Constants
Schematic API Constants reference Schematic API Constants Internal Unit constants cUnits : Array [TUnit] Of TDynamicString = ('mil', 'mm', 'in', 'cm', '', 'm', 'AutoImperial', 'AutoMetric'); cUnitSystems : Array[TUnitSystem] Of TUnitSet = ([eMil, eIN, eDX
Page: Schematic API Design Objects Interfaces
Schematic API Design Objects Interfaces Reference Schematic API Design Objects Interfaces ISch_BasicContainer Interface Overview The ISch_BasicContainer interface represents as a parent object or a child object for a schematic object in Altium Designer. A
Page: Schematic API Functions
Schematic API functions reference. Schematic API Functions SchServer Interface Function SchServer : ISch_ServerInterface; Description The SchServer function returns the interface of the loaded Schematic Editor module in Altium Designer. To work with Schem
Page: Schematic API Overview
Schematic API Overview Object Interfaces Basically an interface is simply a list of methods that a class declares that it implements. That is, each method in the interface is implemented in the corresponding class. Interfaces are declared like classes but
Page: Schematic API System Interfaces
Schematic API System Interfaces reference Schematic API System Interfaces IConnection Interface Overview The IConnection interface represents whether the wire or bus connection has a manual junction on it or not, with location, wire or bus objects count a
Page: Schematic API Types
Schematic API Types reference Schematic API Types The enumerated types are used for many of the schematic interfaces methods which are covered in this section. For example the ISch_Port interface has a ConnectedEnd property which returns a TPortConnectedE
Page: Schematic Arc
Description An arc is a non-electrical drawing primitive. It is essentially a curved line segment which can be used when, for example, creating graphical symbols, custom sheet borders and title blocks. Availability Arcs are available for placement in both
Page: Schematic Bezier
Description A Bezier curve is a non-electrical drawing primitive. It is a free-form curved line that can be placed on a schematic sheet. The curve is defined by a series of vertex points that 'pull' the line into a curved shape. Availability Beziers are a
Page: Schematic Bus
Description A bus is an electrical design primitive. It is a polyline object that represents a multi-wire connection. Availability Buses are available for placement in the Schematic Editor only. Use one of the following methods to access the placement com
Page: Schematic Bus Entry
Description A bus entry is an electrical design primitive. It is a special wire at an angle of 45 degrees that is used to connect a wire to a bus line. A bus entry allows you to connect two different nets to the same point on a bus. If this was done using
Page: Schematic C Code Entry
Description A C Code Entry is an electrical design primitive that belongs within a C Code Symbol. A C Code Symbol represents one top-level exported C function, resident in a referenced C source file. The C Code Entries provide the means by which to access
Page: Schematic C Code Symbol
Description A C Code Symbol is an electrical design primitive. Similar in nature to a standard Sheet Symbol, it is used to reference an underlying C source file. More specifically, it represents a single, top-level exported function within that file. Acce
Page: Schematic Comment
Description The comment text field is a non-electrical child object of an electrical design primitive. It is used to provide a description of a placed part, such as the value (220nF) or device type (74HC32). Availability and Placement The comment is autom
Page: Schematic Compile Mask
Description A compile mask is a design directive. It is used to effectively hide the area of the design it contains from the Compiler, allowing you to manually prevent error checking for circuitry that may not yet be complete and you know will generated c
Page: Schematic Compiler Generated Junction
Description A junction is an electrical design primitive. It is a small circular object used to logically join intersecting wires or buses on a schematic sheet. A Compiler generated junction is a junction that is automatically placed by the Auto-junctioni
Page: Schematic Designator
Description The designator text field is a non-electrical child object of an electrical design primitive. It is used to uniquely identify a placed part, thereby distinguishing it from other parts placed not only on the same schematic sheet, but placed acr
Page: Schematic Device Sheet Symbol
Description A Device Sheet Symbol is an electrical design primitive. It is used to represent a Device Sheet and usually contain predefined circuits. A Device Sheet Symbol references a Device Sheet and can be re-used within and across design projects. Devi
Page: Schematic Editing
Editing Multiple Objects Schematic Editing Essentials Using Design Directives in a Schematic Document Using Device Sheets Using Signal Harnesses
Page: Schematic Editing Essentials
This is a general overview of design object placement and editing methods used in the Schematic Editor. Detailed explanations of placing and editing some of the more complex objects, such as wires and parts are also included. Fundamentals of Object Placem
Page: Schematic Ellipse
Description An ellipse is a non-electrical drawing primitive that can be placed on a schematic sheet. It can be filled or unfilled. Availability Ellipses are available for placement in both Schematic and Schematic Library Editors: Schematic Editor Choose
Page: Schematic Elliptical Arc
Description An elliptical arc is a non-electrical drawing primitive. It is essentially an open circular or elliptical curve that can be placed on a schematic sheet. Availability Elliptical arcs are available for placement in both Schematic and Schematic L
Page: Schematic Filter Panel
Function The SCH Filter panel allows you to construct filters through the creation of logical queries. A defined filter can then be applied to the active schematic document, or all open schematic documents, allowing you to select and edit multiple objects
Page: Schematic Graphic
Description A graphic object is a non-electrical drawing primitive. It is essentially a container for an image file that can be imported and placed onto a schematic sheet. The image associated with a graphic object can either be linked or embedded. Availa
Page: Schematic Harness Connector
Description A Harness Connector object is an electrical drawing primitive. It is essentially a container to group various signals together to form a Signal Harness including buses and wires. A Harness Connector is defined by the Harness Type. Availability
Page: Schematic Harness Entry
Description A Harness Entry is an electrical design primitive that is placed within a Harness Connector. A Harness Entry is the connection point through which actual nets, buses and Signal Harnesses are combined to form a higher level Signal Harness. Avai
Page: Schematic IEEE Symbols
Description IEEE symbols are non-electrical drawing primitives. They are used for representing logic functions or devices. These symbols enable users to understand the logic characteristics of these functions or devices without requiring specific knowledg
Page: Schematic Inspector Panel
Function The SCH Inspector panel enables you to interrogate and edit the properties of one or more design objects in the active schematic document (or all open schematic documents). Used in conjunction with appropriate filtering, the panel can be used to
Page: Schematic Instrument Probe
Description An instrument probe is a design directive. It instructs the system to connect the net to which it is attached directly to the monitoring instrument (e.g. a logic analyzer) without having to explicitly wire that net up through the design hierar
Page: Schematic Library Panel
Function The SCH Library panel enables you to peruse through, and make changes to, the components stored in the active schematic library document. The panel also offers the ability to pass on any changes made to components in the library, directly to the
Page: Schematic Line
Description A line is a non-electrical drawing primitive. Lines are used for adding reference information to a document, such as building graphical symbols, custom sheet borders and title blocks. Availability Line objects are available for placement in bo
Page: Schematic List Panel
Function The SCH List panel allows you to display design objects from one or more documents in tabular format, enabling you to quickly inspect and/or modify object attributes. When used in conjunction with the SCH Filter panel, it enables you to display j
Page: Schematic Manual Junction
Description A junction is an electrical design primitive. It is a small circular object used to logically join intersecting wires or buses on a schematic sheet. A manual junction allows you to create a connection between crossed wires or buses, by placing
Page: Schematic Net Label
Description A wire is an electrical design primitive. Wires that join electrical objects (such as component pins and ports) create what is called a Net. These nets will be assigned system-allocated name unless there is a net label placed on the wire, over
Page: Schematic No ERC
Dyrektywa No ERC The different symbol styles of the No ERC directive. Description The No ERC object is a design directive. This directive is placed on a node in the circuit to suppress reported warning and/or error violation conditions that are detected w
Page: Schematic Note
Description A note is a non-electrical drawing primitive. It is used to add informational or instructional text to a specific area within a schematic, in a similar vain to that of commenting a program's source code. The note is a resizable rectangular are
Page: Schematic Object Reference
Select an object to learn more about its properties and placement. Arc Bezier Bus Bus Entry C Code Entry C Code Symbol Comment Compile Mask Compiler Generated Junction Designator Device Sheet Symbol Ellipse Elliptical Arc Graphic Harness Connector Harness
Page: Schematic Off Sheet Connector
Description An off sheet connector is an electrical design primitive. Off sheet connectors are used to connect nets across multiple schematic sheets that are descended from the same parent sheet symbol. Availability Off sheet connectors are available for
Page: Schematic Parameter
Description A parameter is a non-electrical child object of an electrical design primitive or design directive. It is a user-definable object that allows you to add additional information to a design object supporting the use of parameters (e.g. a part).
Page: Schematic Parameter Set
Description A Parameter Set is a design directive. It is essentially a container for one or more parameters, which can be associated to a net object within a schematic design. Availability Parameter sets are available for placement in the Schematic Editor
Page: Schematic Part
Description A part is an electrical design primitive. It is a schematic symbol that represents an electronic device, such as a resistor, switch, operational amplifier, IC, etc. Parts are stored within components in schematic component libraries (*.SchLib)
Page: Schematic Pie Chart
Description A pie chart is a non-electrical drawing primitive. It is a circular sector graphic element that can be placed on a schematic sheet. It can be filled or unfilled. Availability Pie charts are available for placement in both Schematic and Schemat
Page: Schematic Pin
Description A pin is an electrical design primitive. Pins give a part its electrical properties and define connection points on the part for directing signals in and out. Availability Pins are available for placement in the Schematic Library Editor only.
Page: Schematic Pin Customization
回路図ピンのカスタマイズ    Schematic Enhancements  When it comes to the design of library components, the most important aspect is the electrical connectivity – provided courtesy of optimally placed pins. And with respect to pins, it is important to have control ove
Page: Schematic Polygon
Description A polygon is a non-electrical drawing primitive. It is a multi-sided graphical object that can be placed on a schematic sheet. A polygon must have at least three sides and can be filled or unfilled. Availability Polygons are available for plac
Page: Schematic Port
Description A port is an electrical design primitive. It is used to make an electrical connection between one schematic sheet and another sheet or sheet symbol in a design using multiple sheets (both flat and hierarchical designs). The name of the port de
Page: Schematic Power Port
Description A power port is an electrical design primitive. It is a special schematic object that lets you easily define a power or ground net. Power ports allow you to conveniently indicate a power net at any location in the design, which can then be con
Page: Schematic Probe
Description A probe is a design directive. It is a special marker which is placed on a schematic sheet to identify nodes for digital simulation during netlist generation. It can also be used to interrogate the status, in real time, of a net connecting to
Page: Schematic Processes
This section covers the Schematic processes and their parameters (if any). Table of Schematic processes AlignObjects process AskForXYLocation process BringObjectToFront process BringObjectToFrontOf process ChangeComponentName process ChangeCurrentTemplate
Page: Schematic Query Functions
This section covers Schematic Query functions used by the Query System in Altium Designer. Alignment Field Description Returns all Note, Port, and Text Frame objects having an Alignment property that complies with the Query. Note: The Alignment property i
Page: Schematic Rectangle
Description A rectangle is a non-electrical drawing primitive. It is a graphic element that can be placed on a schematic sheet and can be filled or unfilled. Availability Rectangles are available for placement in both Schematic and Schematic Library Edito
Page: Schematic Round Rectangle
Description A round rectangle is a non-electrical drawing primitive. Essentially a rectangle object with rounded corners, it is a graphic element that can be placed on a schematic sheet - filled or unfilled. Availability Round rectangles are available for
Page: Schematic Sheet Entry
Description A sheet entry is an electrical design primitive that belongs within a sheet symbol. It is placed within a sheet symbol to designate input/output ports for the symbol. The sheet entries correspond to ports placed in the source schematic sub-she
Page: Schematic Sheet Symbol
Description A sheet symbol is an electrical design primitive. It is used to represent a sub-sheet in a multi-sheet hierarchical design. Sheet symbols include sheet entry symbols, which provide a connection point for signals between the parent and child sh
Page: Schematic Sheet Symbol Designator
Description The sheet symbol designator is a non-electrical child object of an electrical design primitive. It is used to provide a sheet symbol with a meaningful name that will distinguish it from other sheet symbols placed on the same schematic sheet. T
Page: Schematic Sheet Symbol Filename
Description The sheet symbol filename is a non-electrical child object of an electrical design primitive. It provides the link between the sheet symbol and the schematic sub-sheet that the symbol represents. Availability and Placement The sheet symbol fil
Page: Schematic Signal Harness
Description A Signal Harness is an electrical design primitive. It is an abstract connection which combines different signals. Availability Signal Harnesses are available for placement in the Schematic Editor only. Use one of the following methods to acce
Page: Schematic Text Frame
Description A text frame is a non-electrical drawing primitive. It is used to define an area on a schematic to contain textual information. The frame is a resizable rectangular area that can contain multiple lines of text and can automatically wrap and cl
Page: Schematic Text String
Description A text string (also referred to as an annotation) is a non-electrical drawing primitive. It is a single line of free text that can be placed on a schematic sheet. Uses might include section headings, revision history, timing information or som
Page: Schematic Wire
Description A wire is an electrical design primitive. It is a polyline object that forms an electrical connection between points on a schematic and is analogous to a physical wire. Availability Wires are available for placement in the Schematic Editor onl
Page: SCHLIB Filter Panel
Function The SCHLIB Filter panel allows you to construct filters through the creation of logical queries. A defined filter can then be applied to the active schematic library component, or all components in the active schematic library, allowing you to se
Page: SCHLIB Inspector Panel
Function The SCHLIB Inspector panel enables you to interrogate and edit the properties of one or more design objects in the active schematic component (or all components in the active schematic library). Used in conjunction with appropriate filtering, the
Page: SCHLIB List Panel
Function The SCHLIB List panel allows you to display design objects associated with one or more schematic components in tabular format, enabling you to quickly inspect and/or modify object attributes. When used in conjunction with the SCHLIB Filter panel,
Page: Scoping Design Rules
When defining the scope of a design rule - the extent of its application - you are essentially building a query to define the member objects that are governed by the rule. Use the options available in the dialog to build the query required.Depending on wh
Page: Script Access for Instruments (AD10)
Japanese 虚拟仪器的脚本访问(版本 10) Script Access to Instruments Altium Designer supports the ability to control instruments using a NanoBoard Interface instrument. This is the notion of controlled instruments (part of the Connected FPGA Scripts feature), whereby a
Page: Script Examples Gallery Reference
This Script Examples Gallery Reference covers the script examples in the Examples\Scripts folder of your Altium Designer installation. Within the Scripts folder are the subfolders which are organized according to scripting language. For example, DelphiScr
Page: Scripting Breakpoints Panel
Function The Breakpoints panel provides information on all breakpoints that are currently defined in all open script files (irrespective of the parent script project (*.PrjScr) they belong to), as well as providing commands for adding, enabling, disabling
Page: Scripting Call Stack Panel
Function The Call Stack panel enables you to view the chain of procedure/function calls that has led to the current point of execution in the script being debugged. Content and Use As you step-debug your script, the panel will show the name of any functio
Page: Scripting Code Explorer Panel
Function The Code Explorer panel provides a visual summary of all identifiers (variables, functions and procedures) that are used in the active script document (*.pas, *.vbs, *.js, *.tcl, *.bas). Content and Use The identifier information that appears in
Page: Scripting in Altium Designer
You can write a script to automate repetitive tasks or enhance a feature in Altium Designer. The scripting system is composed of two main parts; the Editor and the Debugger. Scripts can be saved in a script project or in a design project. There are differ
Page: Scripting Languages
You can choose one of the scripting languages (DelphiScript, EnableBasic, VB Script or Java Script) from Altium Designer to write and use a script in Altium Designer. Delphi Script Reference Delphi Script KeyWord Enable Basic Reference JScript Reference V
Page: Scripting Object Inspector Panel
Function The Object Inspector panel enables you to interrogate and edit the properties and events of components in the active script form. Content and Use Clicking on a single component on the active script form in the design editor window will select the
Page: Scripting Tool Palette Panel
Function The Tool Palette panel provides a range of visual and non-visual components with which to build script forms when writing scripts using DelphiScript (*.pas), VBScript (*.vbs) or JavaScript (*.js). Content and Use The script form components are di
Page: Scripting Watch List Panel
Function The Watch List panel enables you to create and display a list of watch expressions, allowing you to keep track of variable/expression values as you single-step debug the current script document. Content and Use The panel lists, for each watch tha
Page: SDRAM Interface Clocking for the NanoBoard 2
NB2 + DB30 Xilinx Spartan 3 DaughterBoard 1. Schematic wiring for Xilinx DCM clocks. 2. Shared Memory Port Plugin wiring. NB2 + DB31 Altera Cyclone II DaughterBoard 1. Alteral PLL wiring. 2. Shared Memory Port PlugIn wiring. Step by step Clock manager gen
Page: SDRAM Interface Clocking for the NB3000
NB3000XN 1. Schematic wiring for Xilinx DCM clocks. 2. Shared Memory Port PlugIn wiring. NB3000AL 1. Altera PLL wiring. 2. Shared Memory Port PlugIn wiring Step by step Clock manager generation: NanoBoard 3000 Xilinx version Wishbone Clock and Sdram Memor
Page: Searching in a Vault
Vault の検索   Over time your Vault will grow to contain a large amount of data, which could include many thousands of components, managed sheets and completed designs. There are 2 approaches to finding an Item in a Vault, either by browsing through the fold
Page: Searching the Altium Wiki
Altium Wiki の検索   The fastest way to find what you are looking for in the Altium Wiki is to do a site search. The Altium Wiki will search all content, including attachments. On this page: Quick Search The quick search feature allows you to search the Alti
Page: Server Process Reference
Servers A server provides its services in the Altium Designer environment (the client side). The Client module of the Altium Designer interprets the tasks in terms of processes and then delegates these processes to the appropriate servers. For example whe
Page: Server Process Routines
To execute server processes from a script, you can use process routines provided by Altium Designer's Run Time Library in order to execute these server processes and their parameters. Generally you would just use three ResetParameters, AddStringParameter
Page: Setting Processor Internal Memory Size to any Value
Japanese Altium Designer allows you to set the size of internal memory for a supported 32-bit processor to any value. Rather than selecting from a predefined list of memory sizes, as was the case in the Summer 09 release, you are now able to enter the siz
Page: Setting Rule Priorities
As you create a new rule, it is given a priority setting. This setting defines the order in which multiple rules of the same type are applied when, for example, performing a Design Rule Check. Each new rule you add for the same rule type, will be given th
Page: Sharing a Single Slave Device Between Processors
Figure 1 shows an example of using an Arbiter component to connect two 32-bit processors – a MicroBlaze and a TSK3000A – to external SRAM. Interconnect components are used between each processor and the Arbiter component, for their convenience in handling
Page: Sharing Block RAM between two Processors
Although connection to Block RAM is made simple through use of a Memory Controller configured as a BRAM Controller, access to this type of memory will be inherently slower due to its synchronous nature, and therefore the extra clock cycles involved with a
Page: Sharing Multiple Slave Devices Between Processors
Some FPGA designs may require shared processor access to more than one slave memory or peripheral I/O device. In the OpenBus System, this is catered for by using both an Interconnect component and an Arbiter component, with the Arbiter placed before the I
Page: Sheet Panel
Function The Sheet panel provides a mini-viewer for the active document, allowing you to pan and zoom the actual design document in the design editor window, using the available controls in the panel. Content and Use The main region of the panel contains
Page: Short Circuit
Short-Circuit Description Tests for short circuits between primitive objects on the copper (signal and plane) layers. A short circuit exists when two objects that have different net names touch. Constraints Allow Short Circuit defines whether the target n
Page: Shortcut Keys
Japanese Access to Shortcuts Perhaps the single thing you can do to become more productive in any software environment is to learn the shortcut keys. Keystrokes are more efficient than carefully positioning a mouse over a button or drilling through menus,
Page: Showing Physical Differences - Going Graphical
The Project » Show Differences command provides for detection of the logical differences that exist between (typically) different documents - commonly the source documents in a project with the target PCB. These are component and connectivity comparisons.
Page: Signal Base Value
Description Specifies the maximum voltage level that a signal can settle to in the low state (the base value). Constraints Maximum (Volts) the value for the maximum permissible base value voltage. (Default = 0.000). Rule Classification Unary How Duplicate
Page: Signal Integrity Analysis
Performing Signal Integrity Analyses Putting Signal Integrity in its Place Tutorial - Checking Signal Integrity on an FPGA Design
Page: Signal Integrity Panel
Function The Signal Integrity panel is the control center for performing signal integrity analysis on a design. It enables you to screen all nets in a design, against various defined signal integrity rules, in order to quickly identify problematic nets. T
Page: Signal Integrity Rules
Flight Time- Falling Edge Flight Time- Rising Edge Impedance Overshoot- Falling Edge Overshoot- Rising Edge Signal Base Value Signal Stimulus Signal Top Value Slope - Falling Edge Slope - Rising Edge Supply Nets Undershoot- Falling Edge Undershoot- Rising
Page: Signal Stimulus
Signal Stimulus Description Specifies the characteristics of the stimulus signal used when performing a signal integrity analysis on the design. This is the signal that is injected at each output pin on the net under test. The worst-case result is returne
Page: Signal Top Value
Description Specifies the minimum voltage level that a signal can settle to in the high state (the top value). Constraints Minimum (Volts) the value for the minimum permissible top value voltage. (Default = 5.000). Rule Classification Unary How Duplicate
Page: Silk to Silk Clearance
Creating Design Rules Design Rules Rule Category: Manufacturing Description Checks the clearance between any silkscreen text primitive & any other silkscreen primitive; The check insures that the distance is greater or equal with the value specified by th
Page: Silk To Solder Mask Clearance Design Rule
Silk To Solder Mask Clearance デザインルール   Improved Silk To Solder Mask Clearance Rule Silk To Silk Clearance Minimum Solder Mask Sliver Design Rules Design Rule Checking Rule category: Manufacturing. Rule classification: Binary Silk To Solder Mask Clearance
Page: Silkscreen Over Component Pads
Creating Design Rules Design Rules Rule Category: Manufacturing Description Ensures there is correct clearance between silk screen and copper in component pads which are exposed through openings in the solder mask. This check ensures that the distance is
Page: Sim Data Panel
Function The Sim Data panel enables you to add waveforms from the available source data to the active wave plot. It also allows you to obtain measurement information based on the selected waveform and/or use of measurement cursors. Defining Source Data Wa
Page: Simulation Models and Analyses Reference
This reference details the simulation models and circuit simulation analyses and describes some simulation troubleshooting techniques. Simulation Models The Altium Designer-based Circuit Simulator is a true mixed-signal simulator, meaning that it can anal
Page: SiSoft Quantum-SI Export
Japanese Altium Designer supports saving of PCB layouts to SiSoft's Quantum-SI™ CSV (Comma-Separated Values) file format, enabling fast, accurate signal integrity analysis that supports complex layer stacks, split planes, as well as via and pad stacks. To
Page: Situs Autorouting Essentials
Japanese This article looks at the essentials of the Situs autorouter, with information about board setup, design rules and a summary of the routing passes and routing strategies. The Situs Topological Routerbrings a new approach to the autorouting challe
Page: Slope - Falling Edge
- Falling Edge Description Specifies the maximum allowable slope time on the falling edge of the signal. Falling edge slope is the time it takes for a signal to fall from the threshold voltage (VT), to a valid low (VIL). Constraints Maximum (seconds) the
Page: Slope - Rising Edge
Description Specifies the maximum allowable slope time on the rising edge of the signal. Rising edge slope is the time it takes for a signal to rise from the threshold voltage (VT), to a valid high (VIH). Constraints Maximum (seconds) the value for the ma
Page: Smart PDF
Smart PDF generates a single PDF, documenting either selected documents or the entire project - including schematics, PCB and Bill Of Materials. PDF bookmarks are created for each net and component in the design. Save Smart PDF settings to an OutJob file
Page: SMD Neck-Down
Description Specifies the maximum ratio of the track width to the SMD pad width, expressed as a percentage. Constraints Neck-Down the percentage value for the maximum permissible ratio of track width to SMD pad width. Entering a larger value will allow fo
Page: SMD to Corner
Description Specifies the minimum distance from the edge of the surface mount pad to the first routing corner. Constraints Distance the value for the minimum permissible distance from the SMD pad edge to the start of the first routing corner. (Default = 0
Page: SMD to Plane
Description Specifies the maximum routing length from the center of the surface mount pad to the center of the pad/via connecting to a power plane. Constraints Distance the value for the maximum permissible distance from SMD pad to pad/via connecting to t
Page: SMT Rules
SMD Neck-Down SMD to Corner SMD to Plane
Page: Snap Guide Manager (PCB)
Advanced Snap Management Parent article: Unified Cursor-Snap System The <i>Snap Guide Manager</i> dialog. The Snap Guide Manager dialog provides a centralized location from which to define and manage all Snap Guides for the active PCB document – both Line
Page: Snippets
If your designs often include common 'sections' of circuitry or code, then you will make good use of the Design Snippets feature. A simple and easy to use feature, the Snippets system lets you save any selection of: Circuitry on a single schematic sheet C
Page: Soft Design
ソフトデザイン Altium Designer and the Innovation Station From Idea to Implementation How do I Create an FPGA Design? How do I Create an FPGA Design in 30 Minutes? FPGA Design for Board Level Designers FPGA Design for Embedded Developers 'Soft design' is a term
Page: Soft Design - FAQs
Browse the following areas for answers to various questions that are asked when creating the device intelligence for electronic products using Altium Designer. FPGA Design FPGA-ready Design Components Mapping Bus-based Systems Custom Logic Processor-based
Page: Soft Design FAQs - Bus-based Systems
Use the following links to browse through the frequently asked questions relevant to this area of soft design. Can I use the new signal harness features in FPGA design projects created before the Winter 09 release of Altium Designer? OpenBus System docume
Page: Soft Design FAQs - Custom Logic
How do I use VHDL or Verilog in an FPGA design? How do I create and share an FPGA Core? Use the following links to browse through the frequently asked questions relevant to this area of soft design. For more in-depth, visual answers to commonly posed ques
Page: Soft Design FAQs - FPGA Design
How do I create an FPGA design? How do I build an FPGA design? How do I Choose an FPGA Device? How do I Target FPGA-specific Resources? How do I Include Pre-generated EDIF in my FPGA Design? How do I Transfer Xilinx Coregen IP to Altium Designer? How do I
Page: Soft Design FAQs - FPGA-ready Design Components
What do I need to know about Wishbone? How do I Create and Share an FPGA Core? How do I use VHDL or Verilog in an FPGA Design? Use the following links to browse through the frequently asked questions relevant to this area of soft design. For more in-depth
Page: Soft Design FAQs - Hardware Acceleration
Use the following links to browse through the frequently asked questions relevant to this area of soft design. What is hardware acceleration? <p> How can I use Altium's C-to-Hardware Compilation Technology? In terms of FPGA design within Altium Designer,
Page: Soft Design FAQs - Mapping
How do I target and constrain an FPGA design? How do I setup FPGA IO? How do I use Altium Designer with a Third Party FPGA Development Board? How do I Hook up the JTAG Chains in my Target System? How do I Link and Sync my FPGA and PCB Projects? Use the fo
Page: Soft Design FAQs - Processor-based FPGA Design
How do I Decide which Processor to use? How do I add Peripherals and IO to my Processor? How do I Access Wishbone Peripherals in Software? How do I Navigate around my Source Code? How do I Reformat the Appearance of my Source Code? How do I Debug my Desig
Page: Soft Design FAQs - Software Platform (and the Software Platform Builder)
Use the following links to browse through the frequently asked questions relevant to this area of soft design. What is a Device Stack? The software platform is all about making hardware devices available to application code through abstract and generic so
Page: Soft Design FAQs - Testing and Debugging
How do I Debug my Design? How do I use instruments in my FPGA design? How do I Setup and use the LAX Instrument? How do I use the Frequency Counter Instrument? How do I use the Signal Generator Instrument? How do I use the Digital IO Instrument? Use the f
Page: Software Platform Builder Tutorial - Build and Download
Tutorial - Getting Started with the Software Platform Builder   First Steps   Create the Software Platform   Write the Application Code   Build and Download   Simplify the Application Code   Now the whole project has been finished and it is ready to be bu
Page: Software Platform Builder Tutorial - Create the Software Platform
Tutorial - Getting Started with the Software Platform Builder   First Steps   Create the Software Platform   Write the Application Code   Build and Download   Simplify the Application Code   To start, we need to add a special document to the embedded proj
Page: Software Platform Builder Tutorial - First Steps
Tutorial - Getting Started with the Software Platform Builder   First Steps   Create the Software Platform   Write the Application Code   Build and Download   Simplify the Application Code   To allow this tutorial to focus on the Software Platform Builder
Page: Software Platform Builder Tutorial - Simplifying the Application Code
Tutorial - Getting Started with the Software Platform Builder   First Steps   Create the Software Platform   Write the Application Code   Build and Download   Simplify the Application Code   In our example keyboard echo design, the C application has sourc
Page: Software Platform Builder Tutorial - Write the Application Code
Tutorial - Getting Started with the Software Platform Builder   First Steps   Create the Software Platform   Write the Application Code   Build and Download   Simplify the Application Code   Now we are ready to write the C source application. Thanks to th
Page: Software Platform Wrapper
Japanese Software Platform Wrapper Use of the Software Platform to develop your Embedded software is a breeze in Altium Designer, with the Software Platform Wrapper. When you compile your Embedded project, a new header file and C file are automatically ge
Page: Solder Mask Expansion
The shape that is created on the solder mask layer at each pad and via site is the pad or via shape, expanded or contracted radially by the amount specified by this rule. Constraints Expansion the value applied to the initial pad/via shape to obtain the f
Page: Source model limitations
When blank models of pcb boards are imported into Altium Designer, the models that contain large radius arcs are susceptible to bad approximation of these arcs when the pcb document board shape is defined from these models. The reason is the fixed numberi
Page: Specifying Components for an Assembly Variant
Whether adding a new assembly variant or editing an existing one, the job becomes one of definition - which of the original design components to include on the variant and any changes to those components as appropriate to the purpose of the variant.  The
Page: Specifying the Device and Mapping the FPGA Pins
Having made the physical connections required to interface your development board to the Altium Designer Software, you can now prepare an FPGA design so it can be programmed into the target FPGA. To do this you need to: Specify the target FPGA device. Imp
Page: Specifying the Target Board
To define the target board upon which the physical FPGA device resides, simply add the following constraint group to your constraint file: Record = Constraint | TargetKind=PCB | TargetId=My Third Party Development Board where, TargetId specifies the name
Page: Specifying too few Decode Bits
For this example, let's assume the following devices are attached to a processor via an Interconnect component: Port m0 – port peripheral (GPIOA), with base address 0xFF00_0000 Port m1 – port peripheral (GPIOB), with base address 0xFF10_0000 Port m2 – por
Page: Specifying too many Decode Bits
For this example, let's assume the following devices are attached to a processor via an Interconnect component: Port m0 – port peripheral (GPIOA), with base address 0xFF00_0000 Port m1 – port peripheral (GPIOB), with base address 0xFF70_0000 For simplicit
Page: SPI Background
The SPI bus is a full-duplex, synchronous serial data link, that provides an efficient, low-cost communications solution. Like I2C, SPI provides good support for communications with low-speed peripheral devices, though is capable of higher data speeds tha
Page: SPI Communications on the Desktop NanoBoard NB2DSK01
After JTAG, the second most important communications system on Altium's Desktop NanoBoard NB2DSK01 involves communications with devices over the Serial Peripheral Interface (SPI) bus. Use the following linked pages to take a closer look at how the SPI bus
Page: SPI Communications on the NanoBoard 3000
After JTAG, the second most important communications system on the NanoBoard 3000 involves communications with devices over a Serial Peripheral Interface (SPI) bus. In part, SPI communications on the NanoBoard 3000 is similar to that found on the NanoBoar
Page: SPICE Model Creation from User Data
In order to simulate a circuit design using Altium Designer's Mixed-Signal Circuit Simulator, all components in the circuit need to be simulation-ready – that is, they each need to have a linked simulation model. The type of model and how it is obtained w
Page: Standard Dimension
Angular Dimension Baseline Dimension Center Dimension Datum Dimension Leader Dimension Linear Dimension Linear Diameter Dimension Radial Dimension Radial Diameter Dimension Description A standard dimension is a group design object. It places dimensioning
Page: Static Code Analysis - CERT C Secure Code Checking
Japanese 静态代码分析 - CERT的C安全代码检查 CERT Code Checking The high-level C code written for an embedded software project can sometimes be as varied, in style and implementation, as the developer writing it. From an organization's perspective, it is often preferab
Page: Step Exports
Chinese *Altium Designer can export* whole populated boards and associated free models if desired. For the most part, populated board exports are looked at here as many third party CAD tools are utilised in analytics of such a whole product. STEP export f
Page: Storage Manager Panel
Figure 1. The Storage Manager Panel with right click commands. Function The Storage Manager panel is implemented as a workspace panel, accessible by clicking on the System button at the bottom of the application window. The Storage Manager allows you to n
Page: Streamlining Processor-based FPGA Design with the OpenBus System
A complex processor-based design, built on a schematic sheet only, can quickly become over-sized and hard to read. The design on the schematic also suffers from an inherent level of complexity, brought about by having to 'stitch' the bus interfaces of the
Page: String
Description A string is a primitive design object. It places text on the selected layer in a variety of display styles and formats, including popular barcoding standards. As well as user-defined text, "special strings" can be used to place board or system
Page: Stub FPGA Project - Passing Changes to the FPGA Designer
With the PCB project linked to the Stub FPGA project, the PCB Designer can carry out changes to signal characteristics or perform pin swapping in the PCB document and pass these changes to the Stub FPGA project as normal, using the FPGA Workspace Map dial
Page: Stub FPGA Project - Passing Changes to the PCB Designer
When design changes have been made to the Master FPGA design project, they need to be passed back to the PCB Designer. Once again, the key to synchronicity between the two (remote) projects is the Stub FPGA project. For more details on the types of change
Page: Stylesheet assets
Attached to this page are assets and resources relating to the Altium Wiki theme. These attachments are not intended to be used when editing pages
Page: Supplier Search Panel
Main article: Live Links to Supplier Data Supplier Search panel. The Supplier Search panel provides the interface to the live supplier data – a direct portal to parts databases provided through supplier web services. Searching for a Supplier Item Use the
Page: Supply Nets
Description Identifies a supply net and specifies its voltage (or set of nets using the net class scope). Constraints Voltage the voltage value for the net(s) falling under the scope (full query) of the rule. (Default = 0.000V). Rule Classification Unary
Page: Support Container
Subsection
Page: Support for Atmel Touch Controls
Atmel タッチコントロールのサポート 对于 Atmel Touch Controls 的支持 Support for Atmel Touch Controls How many of us got into electronics because we were drawn by the myriad of knobs, lights and other suitably gadget-centric controls? Fast forward a good few years and that a
Page: Support for Microchip Touch Controls
Microchip タッチコントロールのサポート    Support for Microchip mTouch Extending its support for the use of touch controls in designs, Altium Designer provides support for creating planar capacitive sensor patterns on your PCB, for use with the range of Microchip® mTou
Page: Support for PSpice Models in Altium Designer
This application note provides information on the level of support available for using PSpice® models when performing circuit simulations in Altium Designer.   The PSpice® simulation model format is the format of choice for many device manufacturers. Alti
Page: Support for Running Altium Designer on Windows 7
Windows 7 で Altium Designer をサポート Support for Windows 7 As more companies continue to adopt Windows 7 as their operating system of choice, software packages that have performed contently in the Windows XP arena must also now cater for users of the new sys
Page: Supported Altera Architectures
The system supports the latest Altera FPGA technology and includes both FPGA and PCB schematic library support. Table 1 summarizes the supported device technologies and the available library support. Table 1. Supported Altera devices and corresponding lib
Page: Supported Xilinx Architectures
The system supports the latest Xilinx FPGA technology and includes both FPGA and PCB schematic library support. Table 1 summarizes the supported device technologies and the available library support. Table 1. Supported Xilinx devices and corresponding lib
Page: Synchronizing Manually Linked FPGA and PCB Projects
Synchronization of the two linked projects is carried out and maintained by establishing a link between the top-level ports in the FPGA project – specified in the relevant constraint file – and the corresponding pins on the FPGA component schematic. Linki
Page: System Query Functions
This section covers System Query functions (mathematical functions) in Altium Designer. These System Query functions can be used to calculate values and be used for other Query functions. ABS Arithmetic Function Description This function returns a (real)
Page: System Requirements
システム要件   Ensure that your computer meets the system requirements listed below, prior to installing the Altium Designer software. Recommended System Requirements Windows 7 (32-bit or 64-bit) ~ Intel® Core™2 Duo/Quad 2.66GHz (or faster) processor or equival

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Page: Technical Reference - FPGA API
This Reference provides a concise reference of the FPGA API as part of the Altium Designer Run Time Library. The FPGA Application Programming Interface reference covers interfaces for FPGA objects in the FPGA Object Model for the Altium Designer applicati
Page: Technical Reference - Integrated Library API
This reference provides a concise reference of the Integrated Library API as part of the Altium Designer Run Time Library. The Integrated Library Application Programming Interface reference covers the Integrated Library interface objects. Integrated Libra
Page: Technical Reference - PCB API
The PCB Application Programming Interface (API) reference details the object interfaces for PCB objects such as PCB documents and PCB design objects. PCB API, PCB Object Model and Functions The PCB Application Programming Interface consists of the PCB Obj
Page: Technical Reference - Schematic API
The Schematic Application Programming Interface (API) reference details the object interfaces for schematic objects such as schematic documents and schematic design objects. The Schematic API is defined in the RT_Schematic unit which is embedded in the sc
Page: Technical Reference - System API
This reference provides a concise reference of the Altium Designer low level system API as part of the Altium Designer Run Time Library. The System Reference contains low level Application Programming Interface information that can be used for scripting a
Page: Technical Reference - Workspace Manager API
This reference provides a concise reference of the Workspace API as part of the Altium Designer Run Time Library. The WorkSpace Manager Application Programming Interface reference covers the Workspace manager object interfaces from the Workspace Manager O
Page: TERMINAL - Accessible Internal Registers
The following sections detail the internal registers for the Terminal module. Under the bonnet, the device uses the same register addresses as those for the WB_UART8. However, only the registers and bits pertinent to the function of the Terminal module ar
Page: TERMINAL - Block Diagram
Figure 1 shows a high-level block diagram for the TERMINAL device. Figure 1. TERMINAL block diagram.
Page: TERMINAL - Host to Controller Communications
Communications between a 32-bit host processor and the Terminal module are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessibl
Page: TERMINAL - Interrupts
The Terminal module generates two interrupts – one each catering for the transmit and receive sections of the device. In terms of transmission, an interrupt will be generated if the Transmit Buffer becomes empty – flagging to the processor that there is n
Page: TERMINAL - Operational Overview
Once the design is processed and downloaded into the physical FPGA device, the instrument can be used. Displays and controls for the instrument can be found on the device's associated instrument panel. This panel enables you to effectively use the instrum
Page: TERMINAL - Pin Description
The following pin description is for the device when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interface. Table 1. TERMINAL pin description. <table cl
Page: Terminal Module
Figure 1. Terminal Module. Console I/O is a common way of debugging processor systems. The Terminal module (TERMINAL) provides you with a debug console with which to interact with your system directly. It allows you to type text directly in its associated
Page: Test Point Output Options
Altium Designer includes a dedicated Testpoint report generator. The Testpoint report can be generated in three different formats, including IPC-D-356A, and is configured using the Testpoint Report Setup dialog. The Testpoint Report Setup Dialog Testpoint
Page: Testing and Debugging
Japanese How do I Debug my Design? How do I use instruments in my FPGA design? How do I Setup and use the LAX Instrument? How do I use the Frequency Counter Instrument? How do I use the Signal Generator Instrument? How do I use the Digital IO Instrument?
Page: Testing the PC to NanoBoard Connection
Once you have connected the NB2DSK01 to your PC, you should check that the system software can also connect to the NanoBoard. To do this, first start Altium Designer (if not started already). The first time Altium Designer is run, a dialog will appear ask
Page: Testpoint Rules
Main articles: Design Rules, Testpoint System To implement a successful testpoint scheme – where all defined testpoints can be accessed and used as part of the bare-board and/or in-circuit testing – governing constraints must be put in place. To this end,
Page: Testpoint System
Testpoints/Testpoint Manager  Testing is an important part of the board manufacturing process. After fabrication, the board is typically tested to ensure no short or open circuits. Once fully populated with all its components, a board is often tested agai
Page: Texture Mapping Support on 3D Models
Often you would like to increase the realism of components in your 3D views without needing to build complex models in an MCAD environment. The Winter 09 release of Altium Designer helps with this problem by allowing images to be texture mapped onto the t
Page: TFT LCD Panel - Bootstrapping the Daughter Board FPGA
The Desktop NanoBoard NB2DSK01 provides the ability to bootstrap the physical FPGA device, on the currently inserted daughter board, at power-up. To access boot controls (Figure 1), from the Home screen of the GUI touch the icon, followed by the icon. Fig
Page: TFT LCD Panel - Browsing Flash Memory and SD Card Content
The GUI provides a screen for browsing the file content of both the NB2DSK01's common-bus Flash memory and also an SD card currently inserted into the motherboard's SD card reader. To access this screen, simply touch the icon on the GUI's Home screen. Fig
Page: TFT LCD Panel - Bypassing JTAG Devices
With the NanoBoard-NB1, if a user board connected to the NanoBoard did not make use of, or support, the Soft JTAG chain, the TDI_SOFT and TDO_SOFT pins had to be connected at the header, in order for the chain not to be broken. With the Desktop NanoBoard
Page: TFT LCD Panel - Changing System Clock Frequency
The NB2DSK01 motherboard provides an on-board system clock generator in the form of the SPI-compatible ICS307-02 device. The frequency of the programmable clock output from this device can be changed directly through the GUI. To access clock frequency-rel
Page: TFT LCD Panel - Downloading Example Designs Stored on an SD Card
When an SD memory card is inserted into the NB2DSK01 motherboard's SD card reader, the icon becomes enabled on the Home screen of the GUI. Touch this icon to access the Examples sub-screen. Figure 1. Example designs. This screen of the GUI lists all EXAMP
Page: TFT LCD Panel - Driving the GUI
Navigation and selection on the TFT LCD panel is simply a case of touch-and-go. This facility is provided courtesy of the panel's touch screen layer. Use your finger, or the supplied stylus, to touch icons and descend into sub-screens of the GUI, which co
Page: TFT LCD Panel - GUI Options
To access options for the GUI, from the Home screen of the GUI touch on the icon, followed by the icon on the sub-screen that appears. The following options are available: Enable Screen Saver – use this option to enable the automatic screen saver. Screen
Page: TFT LCD Panel - Real Time Clock (RTC)
The GUI contains a screen for viewing/modifying the current date and time. This information is sourced from the NB2DSK01 motherboard's DS1391U-33 device – an SPI-compatible real-time clock (RTC). To access clock controls (Figure 1), from the Home screen o
Page: TFT LCD Panel - Sharing the GUI
The TFT LCD panel on the NB2DSK01 is used by the firmware, to present the interactive GUI, but it can also be used by a design running on the daughter board FPGA. When you program the FPGA with a design that utilizes the panel, it will automatically assum
Page: TFT LCD Panel - Test Routines
A variety of test routines can be performed from the TFT LCD panel, specifically testing the integrity of key elements of the NB2DSK01 motherboard, including the host LEDs and the generic user switches. Test routines (Figure 1) are accessed by pressing th
Page: The Altium Designer Environment
Chinese Japanese Altium Designer supports all aspects of electronic product development. Altium Designer provides a unified electronic product development environment, catering for all aspects of the electronic development process, including: Front-end de
Page: The Design Explorer (DXP) Integration Platform
Design Explorer (DXP) 統合プラットフォーム   The DXP platform provides the key to integration of the various design tools into the single Altium Designer environment. As part of this integration, its job is to provide consistent user interfaces and enhanced tool-in
Page: The Editor View and the Compiled Documents View
The Schematic Editor has a main design window where all of your designs are drawn and viewed. You will notice each Schematic Document in your project has an Editor tab. The design constructed in the Editor tab is the source for compilation which produces
Page: The FPGA Workspace Map
At this stage, both FPGA and PCB projects have been created and linked. All ports on the FPGA project are linked, by net name, to the PCB project pins and there are no changes needing to be pushed in either direction. The question now is how to manage any
Page: The Hard Devices Chain
The Hard Devices chain (Figure 1) shows all target programmable devices detected by the system. This includes FPGAs resident on daughter board plug-ins, as well as all JTAG devices found on any user boards connected to a NanoBoard in the configuration. An
Page: The JTAG Board File
The content of a JTAG Board file is divided into various sections. The following two sections are common to all files: [FileVersion] – the version of the JTAG Board file [BoardDetails] – includes the name of the board as well as any board ID(s). The latte
Page: The NanoBoard Chain
The NanoBoard chain (Figure 1) includes an icon for each powered-up NanoBoard detected by the system on the corresponding PC port. This chain essentially detects the presence of each NanoBoard's controller device, or NanoTalk Controller. As a result it is
Page: The Nexus Standard
While the JTAG standard was originally designed to allow physical testing of devices during PCB assembly, it has been adapted for a variety of uses, most notably to provide in-circuit programmability to FPGAs. Another use of JTAG has been to provide commu
Page: The PC to NanoBoard Connection
Depending on the version of NanoBoard being used, it is connected to your PC using either a parallel or USB connection. When you start Altium Designer, a driver is loaded that configures the relevant port (parallel or USB) to run as a single multiplexed J
Page: The Schematic Editor
回路図エディタ The Schematic Editor allows you to create, edit, check and print the schematic sheets that make up a design project. All the tools and utilities needed to perform checks for electrical and drafting violations, generate reports and create presentat
Page: The Soft Devices Chain
The Soft Devices chain (Figure 1) shows all Nexus-enabled devices, such as 'soft' processors and virtual instruments, found in each FPGA design project targeting a programmable device in the Hard Devices chain. When you use Nexus components in your design
Page: Third Party Boards - Connection using Altium's USB JTAG Adapter
Altium's USB JTAG Adapter allows you to fully experience the benefits of LiveDesign and interact live with your chosen development board via Altium Designer. Connecting your board Connect the USB JTAG Adapter to your PC using the USB cable supplied, via t
Page: Third Party Boards - Detecting a Connected Board
When a Devices view is accessed (View » Devices Views), depending on the configuration of that view Altium Designer scans the USB and/or Parallel ports to determine what is connected. For a parallel port connection, the software tries to use the mappings
Page: Third Party Boards - Direct Connection using a Third Party Parallel Cable
Although connection using Altium's USB JTAG Adapter (or through a NanoBoard) is the simplest method of interfacing Altium Designer with your development board, direct connection of a development board to the PC can still be made using the parallel port ca
Page: Third Party Boards - Indirect Connection using a NanoBoard
If a NanoBoard is available, the third party development board can be indirectly connected to Altium Designer using one of the NanoBoard's User Board headers, as illustrated in Figure 1. Figure 1. Indirect connection via a NanoBoard. Note: The illustratio
Page: Third Party Boards - Software to Development Board Communications
Communications between Altium Designer and the physical devices on the board is carried out using the technology of the IEEE Boundary Scan Standard 1149.1, more commonly referred to as JTAG. To successfully 'hook-up' your development board to the Altium D
Page: Third Party Boards - Testing a Connected Board
To test that the third party board (and device thereon) has been correctly detected, open the FPGA project that you configured for the board, then open the relevant Devices view (View » Devices Views). If the target FPGA has been correctly specified in th
Page: Third party import problems
Importing to third party CAD tools can present problems when different options are used to control the methods of regeneration of the solids. This page describes some of the known issues and solutions. Exports of Boards and footprint components The Solidw
Page: Third-Party Libraries
Libraries available from this page have been developed and submitted by independent sources external to Altium. As such, Altium Limited takes no responsibility for the accuracy or quality of submitted libraries. It is recommended that particular attention
Page: TMR3_W - Accessible Internal Registers
The following sections detail the internal registers for the TMR3_W that can be accessed from the host processor. Timer Control Register (TCON) Address: 0h Access: Read/Write Value after Reset: 00h This register is used to control operation of the timers
Page: TMR3_W - Block Diagram
Figure 1 shows a high-level block diagram for the TMR3_W component. Figure 1. TMR3_W block diagram. The TMR3_W has two 16-bit registers: Timer A and Timer B. Both registers are further sub-divided into two 8-bit registers – TLA and TLB (low 8 bits); THA a
Page: TMR3_W - Host to Controller Communications
Communications between a 32-bit host processor and the TMR3_W are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible interna
Page: TMR3_W - Pin Description
The following pin description is for the TMR3_W when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be made
Page: TMR3_W - Timer Clocking and Interrupt Output Generation
Figure 1 presents a more detailed block diagram of the TMR3_W, showing the clocking of the two timers and the ultimate generation of the interrupt signal to the host processor – INT_O. Figure 1. Timer clocking and interrupt output generation. As can be se
Page: TMR3_W - Wishbone Dual Timer Unit
Figure 1. TMR3_W - Wishbone Dual Timer Unit. The dual timer unit component (TMR3_W) is used to provide additional functionality to processors that do not inherently contain dedicated timing units. The TMR3_W can be configured as counters or timers and pro
Page: To Do Panel
Function The To-Do panel lists all To-Do items that are currently defined for the active project. A To-Do item is used as a reminder for a task that needs to be carried out in relation to a document at a later stage. Content and Use The panel can list two
Page: Topological Autorouting - Mapping the Changing Space
This paper outlines the limitations of current autorouting technologies when faced with the geometric constraints imposed by advancing component and board design technologies, such as staggered pin and ball grids and irregular shapes, and introduces the c
Page: Track
Description A track is a primitive design object. It is a straight solid-filled line with a defined width. Use tracks wherever you need to define a straight line in the PCB workspace. Tracks are generally placed on a signal layer, while using the Interact
Page: Tracking Down Broken Nets
When a net is not completely routed, it is reported as a violation of the applicable Unrouted Net rule. The net is considered to be broken. The violation details for such a net will show how many sub-nets the net is broken into and the percentage of the n
Page: TRAININGcenter
The TRAININGcenter is the public entry point for all things related to training in Altium Designer. It contains information about upcoming face-to-face training courses, Downloadable versions of the Training manuals and a large library of Training Videos.
Page: Troubleshooting NanoBoard 3000 Connection Problems
If, after completing the NanoBoard 3000 setup and installation procedures, the Devices view shows that the system cannot connect to the NanoBoard or cannot detect the presence of its User FPGA, go through the following steps to try to correct the problem:
Page: Troubleshooting NanoBoard Connection Problems
If, after completing the Desktop NanoBoard NB2DSK01 setup and installation procedures, the Devices view shows that the system cannot connect to the NB2DSK01 or cannot detect the presence of an FPGA on the plug-in daughter board, go through the following s
Page: TSK165x RISC MCU
The TSK165x is instruction set compatible with the PIC16C5X family. All instructions are single cycle, except for program branches which take two cycles.   Supply of this soft core under the terms and conditions of the Altium End-User License Agreement do
Page: TSK3000 Support for Hardware Code Breakpoints
TSK3000 ハードウェアコード ブレークポイントのサポート   The TSK3000A 32-bit RISC processor has been enhanced in Altium Designer 13.0, with added support for configurable hardware code breakpoints. The corresponding TSK3000 Debugger has also been enhanced accordingly, to provid
Page: TSK3000A
Figure 1. TSK3000A 32-bit processor. The TSK3000A is a 32-bit, Wishbone-compatible, RISC processor. Most instructions are 32-bits wide and execute in a single clock cycle. In addition to fast register access, the TSK3000A features a user-definable amount
Page: TSK3000A - Arithmetic Instructions
Arithmetic instructions perform arithmetic operations and store the resulting values in registers. The instruction format can be R-type or I-type. With R-type instructions, the two operands and the result are register values. With I-type instructions, one
Page: TSK3000A - Bitwise Logical Instructions
Logical instructions perform bitwise operations and store the resulting values in registers. The instruction format can be R-type or I-type. With R-type instructions, the two operands and the result are register values. With I-type instructions, one of th
Page: TSK3000A - Comparison Instructions
These instructions compare two registers and, based on the result, set a third register to either true or false (1 or 0). Table 1. Comparison Instructions. <DIV align="center"><b>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Mnemonic&nbsp;&nbsp;&n
Page: TSK3000A - Data Transfer Instructions
Data transfer between memory and general purpose registers (GPRs) is handled using Load and Store instructions. All of these instructions are I-type instructions. The only directly supported addressing mode is base register plus 16-bit signed immediate of
Page: TSK3000A - Generic Instructions
Using the core set of assembly language instructions for the TSK3000A as building blocks, a number of generic instructions (also referred to as pseudo instructions or macros) are defined and supported by the Assembler for the TSK3000A. Each of these gener
Page: TSK3000A - Jump Instructions
Jump instructions change the program flow. These instructions will delay the pipeline by one instruction cycle, however an instruction inserted into the delay slot (the instruction immediately following a jump instruction) can be executed while the instru
Page: TSK3000A - Move Instructions
These instructions move data between the various special function registers (SFRs) – including the HI-LO registers used for multiplication and division – and the general purpose registers (GPRs). Table 1. Move Instructions. <DIV align="center"><b>&nbsp;&n
Page: TSK3000A - Programmable Interval Timer
The TSK3000A includes a programmable interval timer. This is simply a 32-bit counter that is incremented once every clock cycle until it hits the limit value stored in the PIT register. It then resets to zero and starts to count up again. The value in thi
Page: TSK3000A - Relative Branch Instructions
Relative branch instructions change the program flow. These instructions effectively delay the pipeline by one instruction cycle. An instruction inserted into the delay slot (the instruction immediately following a branch instruction) will be executed whi
Page: TSK3000A - Shift Instructions
Shift instructions perform shift operations and store the resulting values in registers. All of these instructions are R-type instructions, with the immediate shift amount stored in the IMM5 field for the immediate shift instructions. Table 1. Shift Instr
Page: TSK3000A - Special Purpose Instructions
There are three special instructions used for breakpoints and exceptions. Table 1. Special Purpose Instructions. <DIV align="center"><b>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Mnemonic&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</b></DIV> <DIV align="center"><b>&nbsp;&nbsp;&nbsp
Page: TSK3000A Additional Registers
The TSK3000A defines the following three special registers that are not part of either the GPR or SFR banks of registers. Program Counter (PC) As a program instruction is executed, the Program Counter will contain the address of the program instruction to
Page: TSK3000A Block Diagram
Figure 1 shows a detailed block diagram for the TSK3000A 32-bit processor. Figure 1. TSK3000A block diagram.
Page: TSK3000A Core Instruction - ADD, ADDU
Instruction:                      Add Word Assembler Format:       add rC, rA, rB Example:                          add $3, $4, $5 Description:                     Adds the contents of GPRs rA and rB and puts the result in GPR rC. Operation:              
Page: TSK3000A Core Instruction - ADDI, ADDIU
Instruction:                      Add Immediate Word Assembler Format:       addi rB, rA, IMM16 Example:                          addi $3, $4, 0x1234 Description:                     Sign-extends the 16-bit immediate value, IMM16, adds it to the contents
Page: TSK3000A Core Instruction - AND
Instruction:                      Bitwise Logical AND Assembler Format:       and rC, rA, rB Example:                          and $3, $4, $5 Description:                     Bitwise logically ANDs the contents of GPRs rA and rB and puts the result in GPR
Page: TSK3000A Core Instruction - ANDI
Instruction:                      Bitwise Logical AND Immediate Assembler Format:       andi rB, rA, IMM16 Example:                          andi $3, $4, 0x1234 Description:                     Zero-extends the 16-bit immediate value, IMM16, bitwise logic
Page: TSK3000A Core Instruction - BEQ
Instruction: Branch On Equal Assembler Format: beq rA, rB, target Example: beq t2, $0, _myfunc Description: Generates a branch target address by adding the address of the instruction in the delay slot to a signed offset (a 16-bit immediate value, IMM16, c
Page: TSK3000A Core Instruction - BGEZ
Instruction: Branch On Greater Than Or Equal To Zero Assembler Format: bgez rA, target Example: bgez $3, _myfunc Description: Generates a branch target address by adding the address of the instruction in the delay slot to a signed offset (a 16-bit immedia
Page: TSK3000A Core Instruction - BGEZAL
Instruction: Branch On Greater Than Or Equal To And Link Assembler Format: bgezal rA, target Example: bgezal $3, _myfunc Description: Generates a branch target address by adding the address of the instruction in the delay slot to a signed offset (a 16-bit
Page: TSK3000A Core Instruction - BGTZ
Instruction: Branch On Greater Than Zero Assembler Format: bgtz rA, target Example: bgtz $3, _myfunc Description: Generates a branch target address by adding the address of the instruction in the delay slot to a signed offset (a 16-bit immediate value, IM
Page: TSK3000A Core Instruction - BLEZ
Instruction: Branch On Less Than Or Equal To Zero Assembler Format: blez rA, target Example: blez $3, _myfunc Description: Generates a branch target address by adding the address of the instruction in the delay slot to a signed offset (a 16-bit immediate
Page: TSK3000A Core Instruction - BLTZ
Instruction: Branch On Less Than Zero Assembler Format: bltz rA, target Example: bltz $3, _myfunc Description: Generates a branch target address by adding the address of the instruction in the delay slot to a signed offset (a 16-bit immediate value, IMM16
Page: TSK3000A Core Instruction - BLTZAL
Instruction: Branch On Less Than Zero And Link Assembler Format: bltzal rA, target Example: bltzal $3, _myfunc Description: Generates a branch target address by adding the address of the instruction in the delay slot to a signed offset (a 16-bit immediate
Page: TSK3000A Core Instruction - BNE
Instruction: Branch On Not Equal Assembler Format: bne rA, rB, target Example: bne $3, $4, _myfunc Description: Generates a branch target address by adding the address of the instruction in the delay slot to a signed offset (a 16-bit immediate value, IMM1
Page: TSK3000A Core Instruction - BREAK
Instruction: Breakpoint Assembler Format: break code Example: break 314 Description: If the OCDS is active then the processor will stop at this point and flush any instructions that have entered the pipeline after the break instruction. Operation: Process
Page: TSK3000A Core Instruction - DIV
Instruction: Divide Word Assembler Format: div rC, rA, rB Example: div $2, $3, $4 Description: Divides the contents of GPR rA by the contents of GPR rB, treating both operands as 32-bit two's complement integers. The quotient word is loaded into special r
Page: TSK3000A Core Instruction - DIVU
Instruction: Divide Unsigned Word Assembler Format: divu rC, rA, rB Example: divu $2, $3, $4 Description: Divides the contents of GPR rA by the contents of GPR rB, treating both operands as 32-bit unsigned positive values. The quotient word is loaded into
Page: TSK3000A Core Instruction - J
Instruction: Jump Assembler Format: j target Example: j _myfunc Description: Generates a jump target address by left-shifting a 26-bit immediate value IMM26 (calculated from the target operand) by two bits and combining the result with the high-order 4 bi
Page: TSK3000A Core Instruction - JAL
Instruction: Jump And Link Assembler Format: jal target Example: jal _myfunc Description: Generates a jump target address by left-shifting a 26-bit immediate value IMM26 (calculated from the target operand) by 2 bits and combining the result with the high
Page: TSK3000A Core Instruction - JALR
Instruction: Jump And Link Register Assembler Format: jalr rA Example: jalr $4 jalr $30, $4 Description: Description: Causes the program to jump unconditionally to the address in GPR rA after a delay of one instruction cycle. The address of the instructio
Page: TSK3000A Core Instruction - JR
Instruction: Jump Register Assembler Format: jr rA Example: jr $3 Description: Causes the program to jump unconditionally to the address in GPR rA after a delay of one instruction cycle. Since instructions must be aligned on a word boundary, the two low-o
Page: TSK3000A Core Instruction - LB
Instruction: Load Byte Assembler Format: lb rB, IMM16(rA) Example: lb $3, 2($5) Description: Generates a 32-bit effective address by sign-extending the 16-bit immediate value, IMM16, and adding it to the contents of GPR rA. It then sign-extends the byte a
Page: TSK3000A Core Instruction - LBU
Instruction: Load Byte Unsigned Assembler Format: lbu rB, IMM16(rA) Example: lbu $3, 2($5) Description: Generates a 32-bit effective address by sign-extending the 16-bit immediate value, IMM16, and adding it to the contents of GPR rA. It then zero-extends
Page: TSK3000A Core Instruction - LH
Instruction: Load Halfword Assembler Format: lh rB, IMM16(rA) Example: lh $3, 2($5) Description: Generates a 32-bit effective address by sign-extending the 16-bit immediate value, IMM16, and adding it to the contents of GPR rA. It then sign-extends the ha
Page: TSK3000A Core Instruction - LHU
Instruction: Load Halfword Unsigned Assembler Format: lhu rB, IMM16(rA) Example: lhu $3, 2($5) Description: Generates a 32-bit effective address by sign-extending the 16-bit immediate value, IMM16, and adding it to the contents of GPR rA. It then zero-ext
Page: TSK3000A Core Instruction - LUI
Instruction: Load Upper Immediate Assembler Format: lui rB, IMM16 Example: lui $3, 0x0123456F + 2 Description: Left-shifts 16-bit immediate value, IMM16, by 16 bits, zero-fills the low-order 16 bits of the word, and puts the result in GPR rB. Operation: r
Page: TSK3000A Core Instruction - LW
Instruction: Load Word Assembler Format: lw rB, IMM16(rA) Example: lw $3, 0($5) Description: Generates a 32-bit effective address by sign-extending the 16-bit immediate value, IMM16, and adding it to the contents of GPR rA. It then loads the word at the m
Page: TSK3000A Core Instruction - MFC0
Instruction: Move From Special Function Register Assembler Format: mfc0 rB, rC Example: mfc0 $3, TBHI Description: Loads the contents of special function register rC into GPR rB. Operation: rB <-- SPR[rC] Instruction Type: R-Type Instruction Fields: rB =
Page: TSK3000A Core Instruction - MFHI
Instruction: Move From HI Assembler Format: mfhi rC Example: mfhi $3 Description: Loads the contents of SFR HI into GPR rC. Operation: rC <-- HI Instruction Type: R-Type Instruction Fields: rC = Register index of destination Encoding: <table class='conflu
Page: TSK3000A Core Instruction - MFLO
Instruction: Move From LO Assembler Format: mflo rC Example: mflo $3 Description: Loads the contents of SFR LO into GPR rC. Operation: rC <-- LO Instruction Type: R-Type Instruction Fields: rC = Register index of destination Encoding: <table class='conflu
Page: TSK3000A Core Instruction - MFTC0
Instruction: Move To Special Function Register Assembler Format: mtc0 rB, rC Example: mtc0 $3, PIT Description: Loads the contents of GPR rB into special function register rC. Operation: SPR[Rc] <-- rB Instruction Type: R-Type Instruction Fields: rB = Ind
Page: TSK3000A Core Instruction - MTHI
Instruction: Move To HI Assembler Format: mthi rA Example: mthi $3 Description: Loads the contents of GPR rA into SFR HI. Operation: HI <-- rA Instruction Type: R-Type Instruction Fields: rA = Index of source GPR Encoding: <table class='confluenceTable'><
Page: TSK3000A Core Instruction - MTLO
Instruction: Move To LO Assembler Format: mtlo rA Example: mtlo $3 Description: Loads the contents of GPR rA into SFR LO. Operation: LO <-- rA Instruction Type: R-Type Instruction Fields: rA = Index of source GPR Encoding: <table class='confluenceTable'><
Page: TSK3000A Core Instruction - MULT
Instruction: Multiply Word Assembler Format: mult rC, rA, rB Example: mult $3, $4, $5 Description: Multiplies the contents of GPR rA by the contents of GPR rB, treating both operands as 32-bit two's complement values. The low-order word of the multiplicat
Page: TSK3000A Core Instruction - MULTU
Instruction: Multiply Unsigned Word Assembler Format: multu rC, rA, rB Example: multu $3, $4, $5 Description: Multiplies the contents of GPR rA by the contents of GPR rB, treating both operands as 32-bit unsigned positive values. The low-order word of the
Page: TSK3000A Core Instruction - NOR
Instruction: Bitwise Logical NOR Assembler Format: nor rC, rA, rB Example: nor $3, $4, $5 Description: Bitwise logically NORs the contents of GPR rA with the contents of GPR rB, and loads the result in GPR rC. Operation: rC <-- rA NOR rB Instruction Type:
Page: TSK3000A Core Instruction - OR
Instruction: Bitwise Logical OR Assembler Format: or rC, rA, rB Example: or $3, $4, $5 Description: Bitwise logically ORs the contents of GPR rA with the contents of GPR rB, and loads the result in GPR rC. Operation: rC <-- rA OR rB Instruction Type: R-Ty
Page: TSK3000A Core Instruction - ORI
Instruction: Bitwise Logical OR Immediate Assembler Format: ori rB, rA, IMM16 Example: ori $3, $4, 0x1234 Description: Zero-extends the 16-bit immediate value, IMM16, bitwise logically ORs the result with the contents of GPR rA, and loads the result in GP
Page: TSK3000A Core Instruction - RFE
Instruction: Restore From Exception Assembler Format: rfe Example: mfc0 t1, COP_ExceptionReturn j t1 rfe Description: Copies the control register bits for previous interrupt mask mode and previous user mode (IEp and UMp) to the current mode bits (IEc and
Page: TSK3000A Core Instruction - SB
Instruction: Store Byte Assembler Format: sb rB, IMM16(rA) Example: sb $3, 2($5) Description: Generates a 32-bit effective address by sign-extending the 16-bit immediate value, IMM16, and adding it to the contents of GPR rA. It then stores the least signi
Page: TSK3000A Core Instruction - SH
Instruction: Store Halfword Assembler Format: sh rB, IMM16(rA) Example: sh $3, 2($5) Description: Generates an unsigned 32-bit effective address by sign-extending the 16-bit immediate value, IMM16, and adding it to the contents of GPR rA. It then stores t
Page: TSK3000A Core Instruction - SLL
Instruction: Shift Left Logical Assembler Format: sll rC, rB, IMM5 Example: sll $3, $4, 4 Description: Left-shifts the contents of GPR rB by the number of bits specified by the immediate value, IMM5. Then zero-fills the low-order bits and puts the result
Page: TSK3000A Core Instruction - SLLV
Instruction: Shift Left Logical Variable Assembler Format: sllv rC, rB, rA Example: sllv $3, $4, $5 Description: Left-shifts the contents of GPR rB (by the number of bits designated by the low-order five bits of GPR rA), zero-fills the low-order bits and
Page: TSK3000A Core Instruction - SLT
Instruction: Set On Less Than Assembler Format: slt rC, rA, rB Example: slt $3, $4, $5 Description: Compares the contents of GPRs rB and rA as 32-bit signed integers. If rA is less than rB, a '1' is placed into GPR rC, otherwise GPR rC is loaded with '0'.
Page: TSK3000A Core Instruction - SLTI
Instruction: Set On Less Than Immediate Assembler Format: slti rB, rA, IMM16 Example: slti $3, $4, 0x8764 Description: Sign-extends the 16-bit immediate value, IMM16 and compares the result with the contents of GPR rA, treating both values as 32-bit signe
Page: TSK3000A Core Instruction - SLTIU
Instruction: Set On Less Than Immediate Unsigned Assembler Format: sltiu rB, rA, IMM16 Example: sltiu $3, $4, 0x1234 Description: Sign-extends the 16-bit immediate value, IMM16 and compares the result with the contents of GPR rA, treating both values as 3
Page: TSK3000A Core Instruction - SLTU
Instruction: Set On Less Than Unsigned Assembler Format: sltu rC, rA, rB Example: sltu $3, $4, $5 Description: Compares the contents of GPRs rB and rA as 32-bit unsigned integers. If rA is less than rB, a '1' is placed into GPR rC, otherwise GPR rC is loa
Page: TSK3000A Core Instruction - SRA
Instruction: Shift Right Arithmetic Assembler Format: sra rC, rB, IMM5 Example: sra $3, $4, 4 Description: Right-shifts the contents of GPR rB by the number of bits specified by the immediate value, IMM5. The high-order (IMM5) bits become sign-extended an
Page: TSK3000A Core Instruction - SRAV
Instruction: Shift Right Arithmetic Variable Assembler Format: srav rC, rB, rA Example: srav $3, $4, $5 Description: Right-shifts the contents of GPR rB (by the number of bits designated by the low-order five bits of GPR rA). The high-order bits become si
Page: TSK3000A Core Instruction - SRL
Instruction: Shift Right Logical Assembler Format: srl rC, rB, IMM5 Example: srl $3, $4, 4 Description: Right-shifts the contents of GPR rB by the number of bits specified by the immediate value, IMM5. Then zero-fills the high-order (IMM5) bits and puts t
Page: TSK3000A Core Instruction - SRLV
Instruction: Shift Right Logical Variable Assembler Format: srlv rC, rB, rA Example: srlv $3, $4, $5 Description: Right-shifts the contents of GPR rB (by the number of bits designated by the low-order five bits of GPR rA), zero-fills the high-order (rA 4.
Page: TSK3000A Core Instruction - SUB
Instruction: Subtract Word Assembler Format: sub rC, rA, rB Example: sub $3, $4, $5 Description: Subtracts the contents of GPR rB from GPR rA and puts the result in GPR rC. Operation: rC <-- rA - rB Instruction Type: R-Type Instruction Fields: rA = Regist
Page: TSK3000A Core Instruction - SW
Instruction: Store Word Assembler Format: sw rB, IMM16(rA) Example: sw $3, 2($5) Description: Generates a 32-bit effective address by sign-extending the 16-bit immediate value, IMM16, and adding it to the contents of GPR rA. It then stores the contents of
Page: TSK3000A Core Instruction - SYSCALL
Instruction: System Call Assembler Format: syscall code Example: syscall Description: Raises a System Call exception and passes control to an exception handler. The code field can be used to pass information to an exception handler, but the only way to ha
Page: TSK3000A Core Instruction - XOR
Instruction: Bitwise Logical Exclusive OR Assembler Format: xor rC, rA, rB Example: xor $3, $4, $5 Description: Bitwise logically exclusive-ORs the contents of GPR rA with the contents of GPR rB and loads the result in GPR rC. Operation: rC <-- rA XOR rB
Page: TSK3000A Core Instruction - XORI
Instruction: Bitwise Logical Exclusive OR Immediate Assembler Format: xori rB, rA, IMM16 Example: xori $3, $4, 0x1234 Description: Zero-extends the 16-bit immediate value, IMM16, bitwise logically exclusive-ORs it with the contents of GPR rA, then loads t
Page: TSK3000A Data Organization
Data organization refers to the ordering of the data during transfers. There are two general types of ordering: BIG ENDIAN – the most significant portion of an operand is stored at the lower address LITTLE ENDIAN – the most significant portion of an opera
Page: TSK3000A General Purpose Registers
The TSK3000A has a bank of 32 x 32-bit general purpose registers (GPRs). These registers can be accessed by the R-Type instructions. The register bank can perform two simultaneous reads and one write, from three different addresses within the bank. The fi
Page: TSK3000A Generic Instruction - ABS
Instruction:    Absolute Value Assembler Format Example Translates to... abs rC, rA abs $3, $4 sra $at, rA, 31 xor rC, rA, $at sub rC, rC, $at abs rA abs $4 sra $at, rA, 31 xor rA, rA, $at sub rA, rA, $at
Page: TSK3000A Generic Instruction - ADD
Instruction:    Add <DIV align="center"><b>Assembler Format</b></DIV> <DIV align="center"><b>Example</b></DIV> <DIV align="center"><b>Translates to...</b></DIV> add rC, rB add $3, $4 add rC, rC, rB (with rA = rC) add rC, rA, IMM32 add $3, $2, 0x12345678 s
Page: TSK3000A Generic Instruction - ADDI
Instruction:    Add Immediate <DIV align="center"><b>Assembler Format</b></DIV> <DIV align="center"><b>Example</b></DIV> <DIV align="center"><b>Translates to...</b></DIV> addi rC, IMM16 addi $3, oxFFFF addi rC, rC, IMM16 (where rA = rC)
Page: TSK3000A Generic Instruction - ADDIU
Instruction:    Add Immediate Unsigned <DIV align="center"><b>Assembler Format</b></DIV> <DIV align="center"><b>Example</b></DIV> <DIV align="center"><b>Translates to...</b></DIV> addiu rC, IMM16 addiu $3, oxFFFF addiu rC, rC, IMM16 (where rA = rC)
Page: TSK3000A Generic Instruction - ADDU
Instruction:    Add Unsigned <DIV align="center"><b>Assembler Format</b></DIV> <DIV align="center"><b>Example</b></DIV> <DIV align="center"><b>Translates to...</b></DIV> addu rC, rB addu $3, $4 addu rC, rC, rB (with rA = rC) addu rC, rA, IMM32 addu $3, $2
Page: TSK3000A Generic Instruction - AND
Instruction:    Bitwise Logical AND <DIV align="center"><b>Assembler Format</b></DIV> <DIV align="center"><b>Example</b></DIV> <DIV align="center"><b>Translates to...</b></DIV> and rC, rB and $3, $4 and rC, rC, rB (with rA = rC) and rC, rA, IMM32 and $3,
Page: TSK3000A Generic Instruction - ANDI
Instruction:    Bitwise Logical AND Immediate <DIV align="center"><b>Assembler Format</b></DIV> <DIV align="center"><b>Example</b></DIV> <DIV align="center"><b>Translates to...</b></DIV> andi rC, IMM16 andi $3, oxFFFF andi rC, rC, IMM16 (where rA = rC)
Page: TSK3000A Generic Instruction - B
Instruction:    Branch <DIV align="center"><b>Assembler Format</b></DIV> <DIV align="center"><b>Example</b></DIV> <DIV align="center"><b>Translates to...</b></DIV> b target b Shifter beq $0, $0, target
Page: TSK3000A Generic Instruction - BAL
Instruction:    Branch and Link <DIV align="center"><b>Assembler Format</b></DIV> <DIV align="center"><b>Example</b></DIV> <DIV align="center"><b>Translates to...</b></DIV> bal target bal Shifter bgezal $0, target
Page: TSK3000A Generic Instruction - BEQ
Instruction:    Branch On Equal <DIV align="center"><b>Assembler Format</b></DIV> <DIV align="center"><b>Example</b></DIV> <DIV align="center"><b>Translates to...</b></DIV> beq rA, IMM32, target beq $3, 0x12345678, Shifter li $at, IMM32 beq rA, $at, targe
Page: TSK3000A Generic Instruction - BEQZ
Instruction:    Branch On Equal To Zero <DIV align="center"><b>Assembler Format</b></DIV> <DIV align="center"><b>Example</b></DIV> <DIV align="center"><b>Translates to...</b></DIV> beqz rA, target beqz $3, Shifter beq rA, $0, target
Page: TSK3000A Generic Instruction - BGE
Instruction:    Branch On Greater Than Or Equal <DIV align="center"><b>Assembler Format</b></DIV> <DIV align="center"><b>Example</b></DIV> <DIV align="center"><b>Translates to...</b></DIV> bge rA, rB, target bge $3, $4, Shifter slt $at, rA, rB beq $at, $0
Page: TSK3000A Generic Instruction - BGEU
Instruction:    Branch On Greater Than Or Equal Unsigned <DIV align="center"><b>Assembler Format</b></DIV> <DIV align="center"><b>Example</b></DIV> <DIV align="center"><b>Translates to...</b></DIV> bgeu rA, rB, target bgeu $3, $4, Shifter sltu $at, rA, rB
Page: TSK3000A Generic Instruction - BGT
Instruction:    Branch On Greater Than <DIV align="center"><b>Assembler Format</b></DIV> <DIV align="center"><b>Example</b></DIV> <DIV align="center"><b>Translates to...</b></DIV> bgt rA, rB, target bgt $3, $4, Shifter slt $at, rB, rA bne $at, $0, target
Page: TSK3000A Generic Instruction - BGTU
Instruction:    Branch On Greater Than Unsigned <DIV align="center"><b>Assembler Format</b></DIV> <DIV align="center"><b>Example</b></DIV> <DIV align="center"><b>Translates to...</b></DIV> bgtu rA, rB, target bgtu $3, $4, Shifter sltu $at, rB, rA bne $at,
Page: TSK3000A Generic Instruction - BLE
Instruction:    Branch On Less Than Or Equal To <DIV align="center"><b>Assembler Format</b></DIV> <DIV align="center"><b>Example</b></DIV> <DIV align="center"><b>Translates to...</b></DIV> ble rA, rB, target ble $3, $4, Shifter slt $at, rB, rA beq $at, $0
Page: TSK3000A Generic Instruction - BLEU
Instruction:    Branch On Less Than Or Equal To Unsigned <DIV align="center"><b>Assembler Format</b></DIV> <DIV align="center"><b>Example</b></DIV> <DIV align="center"><b>Translates to...</b></DIV> bleu rA, rB, target bleu $3, $4, Shifter sltu $at, rB, rA
Page: TSK3000A Generic Instruction - BLT
Instruction:    Branch On Less Than <DIV align="center"><b>Assembler Format</b></DIV> <DIV align="center"><b>Example</b></DIV> <DIV align="center"><b>Translates to...</b></DIV> blt rA, rB, target blt $3, $4, Shifter slt $at, rA, rB bne $at, $0, target blt
Page: TSK3000A Generic Instruction - BLTU
Instruction:    Branch On Less Than Unsigned <DIV align="center"><b>Assembler Format</b></DIV> <DIV align="center"><b>Example</b></DIV> <DIV align="center"><b>Translates to...</b></DIV> bltu rA, rB, target bltu $3, $4, Shifter sltu $at, rA, rB bne $at, $0
Page: TSK3000A Generic Instruction - BNE
Instruction:    Branch On Not Equal <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> bne rA, IMM32, target bne $3, 0x12345678, Shifter li $at, IMM32 bne rA, $at, target
Page: TSK3000A Generic Instruction - BNEZ
Instruction:    Branch On Not Equal To Zero <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> bnez rA, target bnez $3, Shifter bne rA, $0, target
Page: TSK3000A Generic Instruction - BREAK
Instruction:    Breakpoint <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> break break break 0
Page: TSK3000A Generic Instruction - DIV
Instruction:    Divide <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> div rA, rB div $3, $4 div $0, rA, rB div rA, IMM32 div $3, 0x12345678 li $at, IMM32 div rA, $at div rC, rA, IMM3
Page: TSK3000A Generic Instruction - DIVU
Instruction:    Divide Unsigned <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> divu rA, rB divu $3, $4 divu $0, rA, rB divu rA, IMM32 divu $3, 0x12345678 li $at, IMM32 divu rA, $at d
Page: TSK3000A Generic Instruction - J
Instruction:    Jump <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> j rA j $3 jr rA
Page: TSK3000A Generic Instruction - JAL
Instruction:    Jump And Link <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> jal rA jal $3 jalr $ra, rA jal rC, target jal rC, Shifter lui $at, @HI(target) addiu $at, $at, @LO(target
Page: TSK3000A Generic Instruction - JALR
Instruction:    Jump And Link Register <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> jalr target jalr Shifter lui $at, @HI(target) addiu $at, $at, @LO(target) jalr $ra, $at jalr rA
Page: TSK3000A Generic Instruction - JR
Instruction:    Jump Register <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> jr target jr Shifter lui $at, @HI(target) addiu $at, $at, @LO(target) jr $at
Page: TSK3000A Generic Instruction - LA
Instruction:    Load Address <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> la rC, target la $3, Shifter see note 1 la rC, target(rA) la $3, Shifter($2) see note 2 Notes If the addre
Page: TSK3000A Generic Instruction - LB
Instruction:    Load Byte <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> lb rC, (rA) lb $3, ($4) lb rC, 0(rA) lb rC, target lb $3, Shifter lui $at, @HI(target) lb rC, @LO(target)($at
Page: TSK3000A Generic Instruction - LBU
Instruction:    Load Byte Unsigned <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> lbu rC, (rA) lbu $3, ($4) lbu rC, 0(rA) lbu rC, target lbu $3, Shifter lui $at, @HI(target) lbu rC,
Page: TSK3000A Generic Instruction - LH
Instruction:    Load Halfword <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> lh rC, (rA) lh $3, ($4) lh rC, 0(rA) lh rC, target lh $3, Shifter lui $at, @HI(target) lh rC, @LO(target)
Page: TSK3000A Generic Instruction - LHU
Instruction:    Load Halfword Unsigned <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> lhu rC, (rA) lhu $3, ($4) lhu rC, 0(rA) lhu rC, target lhu $3, Shifter lui $at, @HI(target) lhu
Page: TSK3000A Generic Instruction - LI
Instruction:    Load Immediate <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> li rC, IMM32 li $3, 0x12345678 see notes Notes The expression should result in a 32-bit integer value in
Page: TSK3000A Generic Instruction - LW
Instruction:    Load Word <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> lw rC, (rA) lw $3, ($4) lw rC, 0(rA) lw rC, target lw $3, Shifter lui $at, @HI(target) lw rC, @LO(target)($at
Page: TSK3000A Generic Instruction - MOVE
Instruction:    Move <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> move rC, rA move $3, $4 or rC, rA, $0
Page: TSK3000A Generic Instruction - MULT
Instruction:    Multiply <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> mult rA, rB mult $3, $4 mult $0, rA, rB mult rA, IMM32 mult $3, 0x12345678 li $at, IMM32 mult rA, $at mult rC,
Page: TSK3000A Generic Instruction - MULTU
Instruction:    Multiply Unsigned <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> multu rA, rB multu $3, $4 multu $0, rA, rB multu rA, IMM32 multu $3, 0x12345678 li $at, IMM32 multu r
Page: TSK3000A Generic Instruction - NEG
Instruction:    Negate <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> neg rC, rA neg $3, $4 sub rC, $0, rA neg rA neg $4 sub rA, $0, rA (with rC = rA)
Page: TSK3000A Generic Instruction - NEGU
Instruction:    Negate Unsigned <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> negu rC, rA negu $3, $4 subu rC, $0, rA negu rA negu $4 subu rA, $0, rA (with rC = rA)
Page: TSK3000A Generic Instruction - NOP
Instruction:    No Operation <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> nop nop sll $0, $0, 0
Page: TSK3000A Generic Instruction - NOR
Instruction:    Bitwise Logical NOR <table class='confluenceTable'><tbody> <tr> <th class='confluenceTh'> <DIV align="center">Assembler Format</DIV> </th> <th class='confluenceTh'> <DIV align="center">Example</DIV> </th> <th class='confluenceTh'> <DIV ali
Page: TSK3000A Generic Instruction - NOT
Instruction:    Bitwise Logical NOT <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> not rC, rA not $3, $4 nor rC, rA, $0 not rA not $4 nor rA, rA, $0 (with rC = rA)
Page: TSK3000A Generic Instruction - OR
Instruction:    Bitwise Logical OR <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> or rC, rB or $3, $4 or rC, rC, rB (with rA = rC) or rC, rA, IMM32 or $3, $2, 0x12345678 see note 2 o
Page: TSK3000A Generic Instruction - ORI
Instruction:    Bitwise Logical OR Immediate <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> ori rC, IMM16 ori $3, oxFFFF ori rC, rC, IMM16 (where rA = rC)
Page: TSK3000A Generic Instruction - ROL
Instruction:    Rotate Left <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> rol rC, rA, IMM5 rol $3, $4, 16 srl $at, rA, 32 - IMM5 sll rC, rA, IMM5 or rC, rC, $at rol rC, rA, rB rol $
Page: TSK3000A Generic Instruction - ROR
Instruction:    Rotate Right <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> ror rC, rA, IMM5 ror $3, $4, 16 sll $at, rA, 32 - IMM5 srl rC, rA, IMM5 or rC, rC, $at ror rC, rA, rB ror
Page: TSK3000A Generic Instruction - SB
Instruction:    Store Byte <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> sb rC, (rA) sb $3, ($4) sb rC, 0(rA) sb rC, target sb $3, Shifter lui $at, @HI(target) sb rC, @LO(target)($a
Page: TSK3000A Generic Instruction - SEQ
Instruction:    Set On Equal To <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> seq rC, rA, rB seq $3, $4, $5 xor rC, rA, rB sltiu rC, rC, 1 seq rC, rA, IMM32 seq $3, $4, 0x12345678 l
Page: TSK3000A Generic Instruction - SGE
Instruction:    Set On Greater Than Or Equal To <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> sge rC, rA, rB sge $3, $4, $5 slt rC, rA, rB xori rC, rC, 1 sge rC, rA, IMM32 sge $3, $
Page: TSK3000A Generic Instruction - SGEU
Instruction:    Set On Greater Than Or Equal To Unsigned <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> sgeu rC, rA, rB sgeu $3, $4, $5 sltu rC, rA, rB xori rC, rC, 1 sgeu rC, rA, IM
Page: TSK3000A Generic Instruction - SGT
Instruction:    Set On Greater Than <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> sgt rC, rA, rB sgt $3, $4, $5 slt rC, rB, rA sgt rC, rA, IMM32 sgt $3, $4, 0x12345678 li $at, IMM32
Page: TSK3000A Generic Instruction - SGTU
Instruction:    Set On Greater Than Unsigned <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> sgtu rC, rA, rB sgtu $3, $4, $5 sltu rC, rB, rA sgtu rC, rA, IMM32 sgtu $3, $4, 0x12345678
Page: TSK3000A Generic Instruction - SH
Instruction:    Store Halfword <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> sh rC, (rA) sh $3, ($4) sh rC, 0(rA) sh rC, target sh $3, Shifter lui $at, @HI(target) sh rC, @LO(target
Page: TSK3000A Generic Instruction - SLA
Instruction:    Shift Left Arithmetic <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> sla rC, rA, IMM5 sla $3, $4, 4 sll rC, rA, IMM5 sla rC, rA, rB sla $3, $4, $5 sllv rC, rA, rB sla
Page: TSK3000A Generic Instruction - SLAV
Instruction:    Shift Left Arithmetic Variable <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> slav rC, rA, rB slav $3, $4, $5 sllv rC, rA, rB slav rC, rB slav $3, $5 sllv rC, rC, rB
Page: TSK3000A Generic Instruction - SLE
Instruction:    Set On Less Than Or Equal To <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> sle rC, rA, rB sle $3, $4, $5 slt rC, rB, rA xori rC, rC, 1 sle rC, rA, IMM32 sle $3, $4,
Page: TSK3000A Generic Instruction - SLEU
Instruction:    Set On Less Than Or Equal To Unsigned <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> sleu rC, rA, rB sleu $3, $4, $5 sltu rC, rB, rA xori rC, rC, 1 sleu rC, rA, IMM32
Page: TSK3000A Generic Instruction - SLL
Instruction:    Shift Left Logical <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> sll rC, rA, rB sll $3, $4, $5 sllv rC, rA, rB sll rC, IMM5 sll $3, 4 sll rC, rC, IMM5 (where rA = rC
Page: TSK3000A Generic Instruction - SLLV
Instruction:    Shift Left Logical Variable <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> sllv rC, rB sllv $3, $4 sllv rC, rC, rB (where rA = rC) Notes SLAV is identical to SLLV and
Page: TSK3000A Generic Instruction - SLT
Instruction:    Set On Less Than <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> slt rC, rB slt $3, $4 slt rC, rC, rB (with rA = rC) slt rC, rA, IMM32 slt $3, $2, 0x12345678 see note
Page: TSK3000A Generic Instruction - SLTI
Instruction:    Set On Less Than Immediate <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> slti rC, IMM16 slti $3, oxFFFF slti rC, rC, IMM16 (where rA = rC)
Page: TSK3000A Generic Instruction - SLTIU
Instruction:    Set On Less Than Immediate Unsigned <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> sltiu rC, IMM16 sltiu $3, oxFFFF sltiu rC, rC, IMM16 (where rA = rC)
Page: TSK3000A Generic Instruction - SLTU
Instruction:    Set On Less Than Unsigned <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> sltu rC, rB sltu $3, $4 sltu rC, rC, rB (with rA = rC) sltu rC, rA, IMM32 sltu $3, $2, 0x1234
Page: TSK3000A Generic Instruction - SNE
Instruction:    Set On Not Equal To <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> sne rC, rA, rB sne $3, $4, $5 xor rC, rA, rB sltu rC, $0, rC sne rC, rA, IMM32 sne $3, $4, 0x123456
Page: TSK3000A Generic Instruction - SRA
Instruction:    Shift Right Arithmetic <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> sra rC, rA, rB sra $3, $4, $5 srav rC, rA, rB sra rC, IMM5 sra $3, 4 sra rC, rC, IMM5 (where rA
Page: TSK3000A Generic Instruction - SRAV
Instruction:    Shift Right Arithmetic Variable <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> srav rC, rB srav $3, $4 srav rC, rC, rB (where rA = rC)
Page: TSK3000A Generic Instruction - SRL
Instruction:    Shift Right Logical <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> srl rC, rA, rB srl $3, $4, $5 srlv rC, rA, rB srl rC, IMM5 srl $3, 4 srl rC, rC, IMM5 (where rA = r
Page: TSK3000A Generic Instruction - SRLV
Instruction:    Shift Right Logical Variable <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> srlv rC, rB srlv $3, $4 srlv rC, rC, rB (where rA = rC)
Page: TSK3000A Generic Instruction - SUB
Instruction:    Subtract <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> sub rC, rB sub $3, $4 sub rC, rC, rB (with rA = rC) sub rC, rA, IMM32 sub $3, $4, 0x12345678 see note 2 sub rC
Page: TSK3000A Generic Instruction - SUBU
Instruction:    Subtract Unsigned <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> subu rC, rB subu $3, $4 subu rC, rC, rB (with rA = rC) subu rC, rA, IMM32 subu $3, $4, 0x12345678 see
Page: TSK3000A Generic Instruction - SW
Instruction:    Store Word <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> sw rC, (rA) sw $3, ($4) sw rC, 0(rA) sw rC, target sw $3, Shifter lui $at, @HI(target) sw rC, @LO(target)($a
Page: TSK3000A Generic Instruction - XOR
Instruction:    Bitwise Logical Exclusive OR <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> xor rC, rB xor $3, $4 xor rC, rC, rB (with rA = rC) xor rC, rA, IMM32 xor $3, $2, 0x123456
Page: TSK3000A Generic Instruction - XORI
Instruction:    Bitwise Logical Exclusive OR Immediate <DIV align="center">Assembler Format</DIV> <DIV align="center">Example</DIV> <DIV align="center">Translates to...</DIV> xori rC, IMM16 xori $3, oxFFFF xori rC, rC, IMM16 (where rA = rC)
Page: TSK3000A Instruction Set
All TSK3000A instructions are binary code compatible. Each instruction comprises a 32-bit word divided into an Opcode, which specifies the instruction type, and one or more operands, which further specify the operation of the instruction. Instruction Form
Page: TSK3000A Interrupt Vector Addresses
Table 1 lists the target vector addresses that are used for each of the TSK3000A's 32 interrupt inputs, configured in Standard and Vectored Modes. In each case, the generic target addresses and default target addresses (based on the default value for EB b
Page: TSK3000A Interrupts and Exceptions
The TSK3000A can generate both hardware exceptions (interrupts) and software exceptions. Hardware Generated Exceptions (Interrupts) The processor has 32 interrupt inputs. Interrupts are wired to the processor's INT_I input pin. Each interrupt can be indiv
Page: TSK3000A Memory Space
The TSK3000A uses 32-bit address buses providing a 4GByte linear address space. All memory access is in 32-bit words, which creates a physical address bus of 30-bits. Memory space is broken into three main areas, as illustrated in Figure 1. Figure 1. Memo
Page: TSK3000A Pin Description
The pinout of the TSK3000A has not been fixed to any specific device I/O – allowing flexibility with user application. The TSK3000A contains only unidirectional pins (inputs or outputs).   The following pin description is for the processor when used on th
Page: TSK3000A Pipeline
The TSK3000A uses a 5-stage execution pipeline structure. The execution of a single instruction is therefore performed in five different stages, as summarized in Figure 1 and detailed in the sections that follow. <table class='confluenceTable'><tbody> <tr
Page: TSK3000A Register Reset Values
Table 1 provides an at-a-glance summary of the values contained in each of the TSK3000A's internal registers after an external system reset has been received on the RST_I input. Table 1. Register reset values. <DIV align="center"><b>Register</b></DIV> <DI
Page: TSK3000A Special Function Registers
Special Function Registers (SFRs) in the TSK3000A are implemented as COP0 registers (Coprocessor 0). They can be read and written (where possible) in a single instruction cycle using the MFC0 and MTC0 instructions, respectively. Table 1 summarizes the spe
Page: TSK51x MCU
The TSK51x is the core of a fast, single-chip, 8-bit microcontroller, which executes all ASM51 instructions and is instruction set compatible with the 80C31. The TSK51x serves software and hardware interrupts, provides an interface for serial communicatio
Page: TSK52x MCU
The TSK52x is an 8-bit embedded controller that executes all ASM51 instructions and is instruction set compatible with the 80C31. Features-at-a-glance Control Unit  8-bit Instruction decoder Reduced instruction cycle time up to 12 times.   Arithmetic-Logi
Page: TSK80x MCU
The TSK80x is a fully functional 8-bit embedded processor which is instruction set compatible with the Zilog Z80CPU.   The TSK80A is instruction set compatible. The TSK80A_D is instruction set compatible with the exception of instruction LD H, H. This opc
Page: Tuning Route Lengths
Two of the core challenges with routing a high speed design are controlling the impedance of the routes, and matching the lengths of critical nets. Impedance controlled routing ensures that the signal that leaves an output pin is correctly received by the
Page: Tutorial - Adding Custom Instrumentation to an FPGA Design
The CUSTOM_INSTRUMENT component is a fully-customizable instrument with which to monitor and control signals within an FPGA design. As part of the instrument's configuration you are able to create your own GUI – the interface that is seen once the design
Page: Tutorial - Checking Signal Integrity on an FPGA Design
Altium Designer's Signal Integrity tool can be used to find the optimum drive and slew settings for specific FPGA pins – for example IO pins used as data lines in an FPGA design. In this tutorial, we are going to answer the question "How hard can I drive
Page: Tutorial - Converting an existing FPGA Design to the OpenBus System
Until now, processor-based FPGA design has typically been performed with a schematic-bias, with all devices in the system layed out on a single schematic sheet. Such designs suffer an inherent complexity, in terms of readability and, more importantly, fro
Page: Tutorial - Creating a Core Component
This tutorial is designed to give you an overview of how to create a core component, synthesize the EDIF and generate a schematic symbol of the core. It covers creating the core project, synthesizing, publishing and generating the symbol in the Schematic
Page: Tutorial - Designing Custom FPGA Logic using C
Altium Designer provides the ability to add custom logic to an FPGA design, where that logic is 'captured' in an underlying C source file. Simply write the functionality required in the comfort of Altium's code-aware C Editor and then sit back as Altium D
Page: Tutorial - Getting Started with Embedded Software
Japanese This tutorial presumes you are familiar with programming in C++, C and/or assembly and have basic knowledge of embedded programming. It contains an overview of the TASKING tools available in Altium Designer. It describes how you can add, create a
Page: Tutorial - Getting Started with FPGA Design
中文 Japanese The Altium Innovation Station – the powerful combination of Altium Designer software and Desktop NanoBoard reconfigurable hardware platform – provides all of the tools and technology needed to capture, implement, test and debug your FPGA desig
Page: Tutorial - Getting Started with PCB Design
Welcome to the world of Altium Designer - a complete electronic product development environment. This tutorial will get you started with creating a PCB project based on an astable multivibrator design. If you are new to Altium Designer then you might like
Page: Tutorial - Getting Started with the Innovation Station
The term Innovation Station represents the powerful combination of the Altium Designer software and the Desktop NanoBoard reconfigurable hardware platform. This combination gives you all of the tools and technology necessary to capture, implement, test an
Page: Tutorial - Getting Started with the Software Platform Builder
Japanese This tutorial will get you started with the Software Platform Builder. Upon completion you will have created an (NanoBoard NB2) application that reads characters from the PS/2 keyboard and echoes them on the Terminal Instrument. To do this the so
Page: Tutorial - Integrating MCAD Objects and PCB Designs
Altium Designer offers high levels of interaction with MCAD data. This means you can import, manipulate and check mechanical design elements against your PCB design directly. MCAD data files can be linked to, which maintains the latest file information wi
Page: Tutorial - Using Profiling Information to Improve Locate Options
Parent article: Profiling Profiling is the process of collecting statistical data about a running application. With these data you can analyze which functions are called, how often they are called and what their execution time is. This tutorial describes
Page: Tutorial - Using Version Control in Altium Designer
チュートリアル - バージョンコントロールの使用 Altium Designer supports Subversion (SVN), Concurrent Versions System (CVS) and other version control systems that support the Microsoft® standard SCC Interface. Because it has direct support for SVN it gives access to many of the
Page: Types of Projects in Altium Designer
Chinese Japanese Altium Designer supports a number of different kinds of projects. Below is a brief description of each. PCB Project (*.PrjPcb) The set of design documents required to manufacture a printed circuit board. The electronic circuit is captured

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Page: Unary and Binary Rule Types
There are two types of design rules - unary and binary. Unary rules apply to one object, or each object in a set of objects. As a consequence, unary design rules have one rule scope. Binary rules apply between two objects, or between any object in one set
Page: Unconnected Pin
Description Detects pins that have no net assigned and no connecting tracks. Constraints None Rule Classification Unary How Duplicate Rule Contentions are Resolved All rules are resolved by the priority setting. The system goes through the rules from high
Page: Undershoot- Falling Edge
Description Specifies the maximum allowable undershoot (ringing above the base value) on the falling edge of the signal. Constraints Maximum (Volts) the value for the maximum permissible undershoot on the falling edge of the signal. (Default = 1.000). Rul
Page: Undershoot- Rising Edge
Description Specifies the maximum allowable undershoot (ringing below the top value) on the rising edge of the signal. Constraints Maximum (Volts) the value for the maximum permissible undershoot on the rising edge of the signal. (Default = 1.000). Rule C
Page: Understanding Constraints
Constraint files are simple documents within the system and can be compiled to add more intelligence to the whole process. A constraint document contains a list of statements, known as constraint groups, each of which targets one or more objects and conta
Page: Understanding Design Annotation
This document explores the process of annotation in Altium Designer - from understanding Schematic, Board Level and PCB Annotation, maintaining design synchronization, to an in-depth coverage of annotating a multi-channel design. Annotation is a routine t
Page: Understanding the Desktop NanoBoard NB2DSK01 Constraint System
The process of mapping or constraining a design to its physical implementation is done by creating constraint files – files that specify implementation detail such as the target device, the port-to-pin mapping, pin IO standards and so on. The minimum info
Page: Understanding the NanoBoard 3000 Constraint System
Main article: NanoBoard 3000 Series The process of mapping or constraining a design to its physical implementation is done by creating constraint files – files that specify implementation detail such as the target device, the port-to-pin mapping, pin IO s
Page: Understanding Version Control, an Introduction
Japanese One of the greatest strengths of an electronic authoring and editing environment is the ease with which you can create and modify a file. This capability means that ideas can be captured, explored and matured quickly – be it code, user documentat
Page: Unified Cursor-Snap System (PCB)
统一的光标捕获系统(PCB) 統一したカーソル-スナップ システム (PCB) Advanced Snap Management Cursor snap is the process whereby the physical mouse cursor's pixel position on the screen drives the position of a 'logical cursor' in the coordinate space of a design document such as a P
Page: Unrouted Net
Description Tests the completion status of each net that falls under the scope (full query) of the rule. If a net is incomplete then each completed section (sub-net) is listed along with the routing completion. The routing completion is defined as: (conne
Page: Updating Altium Designer
Altium Designer の更新 This page was created for releases previous Altium Designer 10. Information about the Update for Altium Designer 10 can be found at the Wiki article A Walk Through...Post-Installation Management of your Altium Designer Solutio In order
Page: Updating the Firmware on the Desktop NanoBoard NB2DSK01
The Desktop NanoBoard NB2DSK01 uses a Xilinx Spartan-3 device (XC3S1500-4FG676C) as the controller for the board. Referred to as the NB2DSK01 - NanoTalk Controller, this device (designated U5) communicates with the host PC using Altium's NanoTalk communic
Page: Updating the Firmware on the NanoBoard-NB1
The NanoBoard firmware is the program that is loaded into the NanoTalk Controller when the board is powered-up. The NanoBoard-NB1 uses a Xilinx Spartan IIE-100K device (XC2S100E) as the controller for the board. Referred to as the NanoTalk Controller, thi
Page: Upgrading a Private License Server
Japanese Main article: Using a Private Server License The latest release of Altium Designer – Altium Designer 10 – does not require a new version of the Private License Server. The Summer 09 version of the server, Build 9.0.0.17655, is compatible with AD1
Page: Upgrading to the Winter 09 release of Altium Designer
This page covers common questions about upgrading your Altium Designer license to the Winter 09 release (for those on versions of Altium Designer previous to this release). For information on upgrading to the latest version of Altium Designer (Altium Desi
Page: USB 2.0 WiFi Adapter Support
Japanese USB WiFi Support Altium Designer provides USB 2.0 WiFi adapter support added through the Software Platform, based on a modified OpenBSD driver framework. Current driver support includes the OpenBSD Ralink chipset drivers run and rum. Utilizing th
Page: USB JTAG Adapter
Japanese Altium's USB JTAG Adapter allows you to fully experience the benefits of LiveDesign and interact live with your chosen development board via Altium Designer. Connecting to third-party boards Connecting your board Using Altium Designer with a Thir
Page: USB JTAG Adapter - Cable Pinouts
Altium's USB JTAG Adapter enables you to utilize JTAG communications – the heart of Altium Designer's LiveDesign methodology – with your chosen third party development board. Closer to home, the adapter enables you to update the normal operational firmwar
Page: Useful Scripts
Page: User Defined From-To
Description User-defined From Tos allow you to create specific net topologies within a design, giving you total control over the arrangement, or pattern, of pin-to-pin connections in a net. They are different to system-generated From Tos, added and arrang
Page: Using a Private Server License
Japanese Używanie licencji typu Private Server Altium Designer's Private Server licensing offers you floating license capability through implementation of your own dedicated Private License Server. Your administrator sets up this central server (also refe
Page: Using a Standalone License
Japanese Używanie licencji typu Standalone Altium Designer's Standalone licensing allows you to effectively manage your own license through use of a Standalone licensing file (*.alf). This file can be saved, copied and backed-up as required. The .alf file
Page: Using Altium Designer with a Third-Party Board
When developing an FPGA design using Altium Designer, the full, feature-rich LiveDesign environment becomes available with the presence of a NanoBoard - an Innovation Station. Many Engineers and Designers however, already possess third-party FPGA developm
Page: Using an On-Demand License
Japanese Używanie licencji typu On-Demand Altium Designer's On-Demand licensing offers you global floating license capability – within the geographic scope of your license and the conditions set out in the EULA – without the need to implement your own ded
Page: Using Components Directly from Your Company Database
会社のデータベースから直接、コンポーネントを使用   This document provides detailed information on using components from a database using Altium Designer's Database Library feature. Altium Designer provides the ability to place components directly from a company database by creat
Page: Using Configurations
Configurations and constraint files can be considered from two different perspectives. Existing Board In the case where the FPGA designer is working with an existing (constructed) PCB, the resources of the board and how they are connected to the FPGA are
Page: Using Design Directives in a Schematic Document
Altium Designer uses directives as instructions to certain parts of the software, in order to achieve the desired outcome. Design directives (to give them their full title) are objects that are placed solely within the confines of schematic sheets. A vari
Page: Using Device Sheets
Japanese Device Sheets simplify the design process by providing modularized and consistent building blocks which can be re-used between projects. Device Sheet Symbols are placed and referenced similarly to components. They function in the same way as Shee
Page: Using Multiple SPI and I2C Devices in a Design
Related article: NanoBoard SPI Communications - Interface Wiring When interfacing to a single common-bus SPI (or I2C) device from an FPGA design, access to the device is straightforward – simply place the specific port component representing the interface
Page: Using Signal Harnesses
The Schematic Editor has been enhanced to include the new concept of Signal Harnesses. Signal Harnesses enable the logical grouping of different signals including buses and wires, for increased flexibility and streamlined design. Wires are used to represe
Page: Using SIMetrix SIMPLIS Circuit Simulation
Catena Software's SIMetrix/SIMPLIS ® is a popular Circuit Simulation package. SIMetrix/SIMPLIS is a combination of two independent circuit simulators: SIMetrix, a SPICE-based simulator with numerous enhancements including custom models for power transisto
Page: Using SPI Flash Memory as Embedded Memory
Related articles: SPI Communications on the NanoBoard NB2, SPI Communications on the NanoBoard 3000 The NanoBoard provides SPI Flash memory for use as embedded memory in an FPGA design. This enables you to load and store an embedded software file that wil
Page: Using the Altium Designer RTL
The Altium Designer Run Time Library (RTL) is composed of Application Programming Interfaces (APIs), specialized classes and system routines. Each API has an Object Model and in turn, the object model is a hierarchical system of object interfaces. These o
Page: Using the Client and Server API
Client and Server Interfaces The client module is represented by its IClient interface object and you have the ability to take a peek into the data structures through this IClient interface. The client maintains a list of loaded servers, opened server doc
Page: Using the Integrated Library API
Integrated Library Interfaces There are different types of libraries in Altium Designer - normal standalone libraries like PCB Libraries and Schematic Libraries, other library types called integrated libraries which contain different libraries bundled tog
Page: Using the PCB API
PCB Editor Interfaces The PCB API allows a programmer to fetch or modify PCB objects and their attributes from a PCB document. The objects shown on a document are stored in its corresponding design database.The PCB interfaces exposed by the PCB editor ref
Page: Using the Schematic API
Schematic Editor Interfaces The Schematic API allows a programmer to fetch or modify Schematic objects and their attributes from a Schematic document. The objects shown on a document are stored in its corresponding design database.The Schematic interfaces
Page: Using the Software Platform Builder
Introduction to the Software Platform   Organization of the Software Platform   Using the Software Platform Builder   Glossary   The Software Platform Builder is the graphical interface that you can use to work with the modules in the Software Platform. T
Page: Utilizing the SPI Flash Memory on the NanoBoard-NB1
The NanoBoard-NB1 provides Serial SPI Flash memory for use as embedded memory in an FPGA design, enabling you to load and store an embedded software file that will be used when the target design is running. One example of where such functionality would pr

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Page: Vault-Based Components
Japanese create a new vault-based component? batch-create multiple vault-based components? import an INTLIB to my vault?(part A) import an INTLIB to my vault?(part B) place components from my vault? see where components have been used? update components i
Page: Vault-Based Domain Models
Vault ベースの領域モデル batch-create multiple vault-based components? Related articles: Vault-Based Components, Altium Vaults From a designer's perspective, a vault-based component gathers together all information needed to represent that component across all des
Page: Vault-Defined Supply Chain Information in BOM
Vault 定義のサプライチェーン情報を BOM へ   Altium Designer provides the ability to include vault-based supply-chain information in your Bill of Materials. This gives you the most realistic 'snap-shot' yet of pricing and availability of the physical, real-world componen
Page: Vault-Driven Electronics Design
Vault によるエレクトロニクス設計 Designing with Altium mini-site An Introduction to Vault-Driven Electronics Design Getting Started with the Vault-Driven Methodology Next Generation Component Management Next Generation Component Management High-Integrity Board Design
Page: Vault-Driven Electronics Design - FAQs
Vault によるエレクトロニクス設計 - FAQ The following links provide access to more detailed information on features and technologies provided as part of Altium's Design Data Management System: Altium Vaults Vaults Panel Items and Item Revisions Item Revision Naming Sch
Page: Vaults Panel
Vault Explorer パネル Parent page: Altium Vaults The <i>Vault Explorer</i> panel gives access to your valuable company data stored in your Altium Vault. Summary The Vault Explorer panel is the primary interface between Altium Designer and a connected Altium
Page: VB Script Reference
This VB Script reference describes the VB Script language used in Altium Designer. Exploring the VB Script Language This Reference details each of the VisualBasic Scripting statements, functions and extensions that are supported in the scripting system. T
Page: Vendor Codes
  3M 3M Abracon ABRA Acme Electric ACME Actel ACTL Advanced Linear Devices AVLD AKM AKM Allegro Microsystems ALEG Altera ALTR Amphenol AMPH AMS AMS Analog Devices ADI Atmel ATML AVX AVX Bel Fuse BELF Bivar BIVR Bosch Sensortech BOSC Bourns BOUR C&K Compon
Page: Vendor Place and Route Software
The task of implementing the design in the actual FPGA is carried out by specialised tools, referred to as place and route tools. These software tools are provided by the FPGA vendors, who with their intimate knowledge of the features available within eac
Page: Vendor Tool Installation
ベンダツールのインストール Before you can build an FPGA design for a targeted device, you must have the appropriate vendor tools installed on your computer. These tools are used to place and route the FPGA design for the target device. The FPGA vendor tools ARE NOT su
Page: Verifying Your Design in Altium Designer
What do designers use as part of their daily arsenal in their approaches to design verification in order to be confident that their design is ready for PCB layout? Verifying that a design is correct is often the most difficult and yet also the most import
Page: Verilog Netlist Output Options
Verilog output options are set up in the Verilog Generation Settings dialog. Verilog output options are set up in the Verilog Generation Settings dialog. Content and Use The Verilog Generation Settings dialog offers the following options when generating o
Page: Version Control Improvements
Revision management of design data using third-party version control systems is a foundation element of Altium Designer's support for Design Team collaboration. Altium Designer Winter 09 includes a number of enhancements in this area. Version number in Sc
Page: Version Control Terminology
Japanese Terminology Check-in To save your working copy of the file into the repository. Referred to as Commit in some version control systems. Check-out To take a copy of a file from the repository into your working folder (sandbox). Typically you will b
Page: VGA32 - Wishbone 32-bit VGA Controller
Figure 1. VGA32 - Wishbone 32-bit VGA Controller. The VGA32 Controller provides a simple, 32-bit interface between a host processor and any VGA-compatible monitor. Taking a processor-generated picture (pixilated) from memory space, the Controller provides
Page: VGA32 Controller - Accessible Internal Registers
The following sections detail the internal registers for the VGA32 Controller, accessible from the host processor. Control Register (CTRL) Address: 0000000000b Access: Read/Write Value after Reset: 0000_0000h This 32-bit register is used to configure and
Page: VGA32 Controller - Block Diagram
Figure 1 shows a high-level block diagram for the VGA32 Controller component. Figure 1. VGA32 Controller block diagram. For information on the internal registers for the VGA32 Controller that can be accessed from the host processor, see Accessible Interna
Page: VGA32 Controller - Color Look-up Tables
Two color look-up tables are available for use with the VGA32 Controller, each of which contain 256 addresses. The two tables form a single contiguous 512 x 32-bit address space: CLUT0 – with address range 100h to 17Fh CLUT1 – with address range 180h to 1
Page: VGA32 Controller - Color output using the NanoBoard-NB1
The R, G and B outputs from the VGA32 Controller are 8 bits in length, supporting 8-bits per pixel (B&W or color). Together, these outputs form the 24-bit RGB value (True Color) required for driving the red, green and blue color guns of the target monitor
Page: VGA32 Controller - Pin Description
The following pin description is for the VGA32 Controller (configured WB_VGA component) when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The
Page: VGA32_16BPP - Wishbone 32-bit VGA Controller with 16bpp Data Support
Figure 1. VGA32_16BPP - Wishbone 32-bit VGA Controller with 16bpp Data Support. The VGA32_16BPP Controller provides a simple, 32-bit interface between a host processor and any VGA-compatible monitor. The Controller fetches 16bpp-formatted data from extern
Page: VGA32_16BPP Controller - Accessible Internal Registers
The following sections detail the internal registers for the VGA32_16BPP Controller, accessible from the host processor. Control Register (CTRL) Address: 0000000000b Access: Read/Write Value after Reset: 0000_0000h This 32-bit register is used to configur
Page: VGA32_16BPP Controller - Block Diagram
Figure 1 shows a high-level block diagram for the VGA32_16BPP Controller component. Figure 1. VGA32_16BPP Controller block diagram. For information on the internal registers for the VGA32_16BPP Controller that can be accessed from the host processor, see
Page: VGA32_16BPP Controller - Color output using the NanoBoard-NB1
The R, G and B outputs from the VGA32_16BPP Controller are 5, 6 and 5 bits in length respectively. Together, these outputs form the 16-bit RGB value required for driving the red, green and blue color guns of the target monitor. On Altium's Desktop NanoBoa
Page: VGA32_16BPP Controller - Pin Description
The following pin description is for the VGA32_16BPP Controller (configured WB_VGA component) when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interface
Page: VGA32_16BPP, VGA32_TFT - External Memory Data Format
When using the VGA32_16BPP or VGA32_TFT 32-bit VGA Controller variants, the color quality is fixed at 16 bits per pixel. The VGA Controller does not create the output RGB value for a pixel through use of a color look-up table – rather the color informatio
Page: VGA32_TFT - Wishbone 32-bit VGA Controller with TFT Interface
Figure 1. VGA32_TFT - Wishbone 32-bit VGA Controller with TFT Interface. The VGA32_TFT Controller provides a simple, 32-bit interface between a host processor and a TFT (Thin Film Transistor) LCD panel. The Controller fetches 16bpp-formatted data from ext
Page: VGA32_TFT Controller - Accessible Internal Registers
The following sections detail the internal registers for the VGA32_TFT Controller, accessible from the host processor. Control Register (CTRL) Address: 0000000000b Access: Read/Write Value after Reset: 0000_0000h This 32-bit register is used to configure
Page: VGA32_TFT Controller - Block Diagram
Figure 1 shows a high-level block diagram for the VGA32_TFT Controller component. Figure 1. VGA32_TFT Controller block diagram. For information on the internal registers for the VGA32_TFT Controller that can be accessed from the host processor, see Access
Page: VGA32_TFT Controller - Pin Description
The following pin description is for the VGA32_TFT Controller (configured WB_VGA component) when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces.
Page: VHDL Breakpoints Panel
Function The Breakpoints panel provides information on all breakpoints that are currently defined in all open VHDL source files (irrespective of the parent FPGA project (*.PrjFpg) they belong to), as well as providing commands for enabling, disabling and
Page: VHDL Code Explorer Panel
Function The Code Explorer panel provides a visual summary of all entities and architectures (and identifiers therein) declared in the active VHDL source document (*.VHD, *.VHDTST) for an FPGA project (*.PrjFpg). Content and Use The identifier information
Page: VHDL Netlist Output Options
VHDL output options are set up in the _VHDL Generation Settings_ dialog. VHDL output options are set up in the VHDL Generation Settings dialog. Content and Use The VHDL Generation Settings dialog offers the following options when generating one or more VH
Page: VHDL Simulation Panel
Function The Simulation panel allows you to browse the VHDL hierarchy of the active FPGA project currently under simulation. For each specific area of the hierarchy - testbench, design under test and component instantiations within the design - you can in
Page: VHDL Synthesis Reference
VHDL is a hardware description language (HDL). It contains the features of a conventional programming language, a classical PLD programming language, and a netlist, as well as design management features. VHDL is a large language and it provides many featu
Page: VHDL Watches Panel
Function The VHDL Watches panel enables you to create and display a list of watch expressions, allowing you to keep track of signal values as you single-step debug the VHDL source code of your FPGA project. Content and Use For each watch that is added, th
Page: Via
Japanese Description A via is a primitive design object. It is used to form an electrical connection between two signal layers of a PCB. Vias are like round pads, which are drilled and usually through-plated when the board is fabricated. Availability Vias
Page: Via Stitching
ビアスティッチング   Stitching Vias Via stitching is a technique used to tie together larger copper areas on different layers, in effect creating a strong vertical connection through the board structure, helping maintain a low impedance and short return loops. In
Page: Via Stitching Enhancements
ビアスティッチングの改善   Via stitching has been enhanced in Altium Designer 13.2, with the addition of a number of features that greatly improve the functionality of the feature. The Via Stitching feature allows regions of copper on different layers to be connected
Page: Vias Under SMD
Description Specifies whether vias can be placed under SMD pads during autorouting. Constraints Allow Vias under SMD Pads specifies whether vias can be placed under the pads of surface mount components. (Default = disabled). Rule Classification Unary How
Page: Video Output Container
Japanese 3D PCB Movie Editor Related article: PCB 3D Video In support of PCB 3D Video output, Altium Designer 10 sees the addition of a new Multimedia output medium – also referred to as the Multimedia Publisher. Used solely for the generation of PCB 3D V
Page: Viewing Data Captured by the Logic Analyzer
Once captured, you can view the sampled data either in tabular format, or as a set of digital and/or analog waveforms. Tabular Display of the Captured Data Captured data, stored in the sample buffer, will appear in the Captured Data region of the LAX pane
Page: Violation
Description A violation object marks an instance in the design where a particular design rule is currently being violated by one or more design objects. The violation itself is highlighted in the workspace through the use of a DRC Error Marker. Availabili
Page: Visual Designer for Embedded GUI
Japanese The development of a Graphical User Interface for your embedded embedded applications has been greatly simplified with the introduction of a Visual Designer for embedded GUI design. The Visual Designer uses the familiar mechanisms for GUI design,
Page: Visualization of Project Variants on the PCB
Japanese Variants Shown in the PCB Editor Altium Designer allows fabrication outputs to be driven by variants. More specifically, this allows you to specify a change to a component's Comment parameter, and that change will be passed through to the fabrica
Page: Visualization of the Route Tool Path
Japanese In the board design world there is actually 2 distinctly different uses of the word routing. There's the routing of the nets across and through the board to connect the various nodes in the net. Then there's the routing, or milling, process that
Page: Voltage Shifting
When connecting a development board directly to the PC via the parallel port, using only a parallel cable, the voltage level of the JTAG signals from the port are at a level of 5V. This level exceeds the safe operating voltage level for signals connected

W

Page: Wave Panel
Function The Wave panel enables you to jump to transitions for the focused waveform, when viewing digital waveforms associated with a logic analyzer instrument. It also allows you to add and remove additional views for selected base waveforms. Content and
Page: Waveform Style Management (Digital Waveform Viewer)
Control over how captured signal information is presented in the Digital Waveform Viewer is taken to the next level in this release, with the waveform style system enhanced to provide a number of additional built-in styles and allowing you to set styles a
Page: WB_ASP - Configurable Wishbone Application Specific Processor
Figure 1. WB_ASP - Wishbone Application Specific Processor. The WB_ASP peripheral is an Application Specific Processor used as a 'container' for C source functions that are implemented in hardware through use of the C-to-Hardware Compiler. Wired into an F
Page: WB_ASP - Configuration
The WB_ASP can be configured after placement on the OpenBus System document, or schematic sheet, using the associated Configure (WB_ASP Properties) dialog (Figure 1). Access to this dialog depends on the document in which you are working: In the OpenBus S
Page: WB_ASP - Interfacing to External Memory
In a design that contains both software and hardware functions, certain variables may be common to the two. Such variables that need to be accessed by the software and hardware can be allocated in shared memory. This could be Block RAM within the FPGA its
Page: WB_ASP - Pin Description
The following pin description is for the WB_ASP when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. Table 1. WB_ASP pin description. <table cla
Page: WB_BOOTLOADER - Accessible Internal Registers
The SPI Bootloader component contains four internal registers that are accessible by software, when the optional SPI Controller port is enabled – CSR, CDIV, DATAOUT, DATAIN. These registers allow the component to be used as an SPI Controller for communica
Page: WB_BOOTLOADER - Block Diagram
Figure 1 shows a high-level block diagram for the WB_BOOTLOADER component. Figure 1. WB_BOOTLOADER block diagram. For information on the internal registers for the WB_BOOTLOADER that can be accessed from the host processor, see Accessible Internal Registe
Page: WB_BOOTLOADER - Configurable Wishbone Flash SPI Bootloader (Version 1)
Figure 1. WB_BOOTLOADER - Configurable Wishbone Flash SPI Bootloader<br>(slave SPI Controller interface enabled). The Flash SPI Bootloader component (WB_BOOTLOADER) provides the ability to automatically load (or bootstrap) from serial Flash memory on the
Page: WB_BOOTLOADER - Configuration
The SPI Bootloader component can be configured after placement on the OpenBus System document, or schematic sheet, using the associated configure dialog (Figure 1). Access to this dialog depends on the document in which you are working: In the OpenBus Sys
Page: WB_BOOTLOADER - Host to Controller Communications
Communications between a 32-bit host processor and the WB_BOOTLOADER are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible
Page: WB_BOOTLOADER - Interfacing
How the SPI Bootloader component is placed and wired within an FPGA design depends on two things: How the device is being used – for bootloading and SPI control, for bootloading purposes only, or purely as an SPI Controller. The method used to build the d
Page: WB_BOOTLOADER - Operational Overview
Provided the starting address in SRAM and the size of transfer are both specified in the configuration dialog for the SPI Bootloader, the bootloading functionality will be automatic upon FPGA design download or subsequent system reset. Transfer from the s
Page: WB_BOOTLOADER - Pin Description
The following pin description is for the WB_BOOTLOADER when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals to th
Page: WB_BOOTLOADER_V2 - Accessible Internal Registers
The SPI Bootloader component contains six internal registers that are accessible by software, when the optional SPI Controller port is enabled – DATA8, DATA16, DATA32, CTRL, STATUS and CDIV. These registers allow the component to be used as an SPI Control
Page: WB_BOOTLOADER_V2 - Block Diagram
Figure 1 shows a high-level block diagram for the WB_BOOTLOADER_V2 component. Figure 1. WB_BOOTLOADER_V2 block diagram. For information on the internal registers for the WB_BOOTLOADER_V2 that can be accessed from the host processor, see Accessible Interna
Page: WB_BOOTLOADER_V2 - Configurable Wishbone Flash SPI Bootloader (Version 2)
Figure 1. WB_BOOTLOADER_V2 - Configurable Wishbone Flash SPI Bootloader (Version 2)<br>(slave SPI Controller interface enabled). The Flash SPI Bootloader component (WB_BOOTLOADER_V2) provides the ability to automatically load (or bootstrap) from serial Fl
Page: WB_BOOTLOADER_V2 - Configuration
The SPI Bootloader component can be configured after placement on the OpenBus System document, or schematic sheet, using the associated configure dialog (Figure 1). Access to this dialog depends on the document in which you are working: In the OpenBus Sys
Page: WB_BOOTLOADER_V2 - Host to Controller Communications
Communications between a 32-bit host processor and the WB_BOOTLOADER_V2 are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessib
Page: WB_BOOTLOADER_V2 - Interfacing
How the SPI Bootloader component is placed and wired within an FPGA design depends on two things: How the device is being used – for bootloading and SPI control, for bootloading purposes only, or purely as an SPI Controller. The method used to build the d
Page: WB_BOOTLOADER_V2 - Operational Overview
Provided the starting address in SRAM and the size of transfer are both specified in the configuration dialog for the SPI Bootloader, the bootloading functionality will be automatic upon FPGA design download or subsequent system reset. Transfer from the s
Page: WB_BOOTLOADER_V2 - Pin Description
The following pin description is for the WB_BOOTLOADER_V2 when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals to
Page: WB_DUALMASTER - Configurable Wishbone Dual Master
Figure 1. WB_DUALMASTER - Configurable Wishbone Dual Master. The WB_DUALMASTER peripheral component provides a simple means of sharing a slave Wishbone device between two masters – for example, sharing a physical memory device between either two processor
Page: WB_DUALMASTER - Configuration
The WB_DUALMASTER component can be configured after placement on the schematic sheet. Simply right-click and choose the command to configure the component from the pop-up menu that appears (e.g. Configure U_DUALMASTER (WB_DUALMASTER) for a component with
Page: WB_DUALMASTER - Interfacing
Figure 1 shows an example of using a configurable Wishbone Dual Master component to connect two 32-bit processors (TSK3000As) to the Static RAM located on a daughter board. On the Master side, Wishbone Interconnect components have been used to connect eac
Page: WB_DUALMASTER - Pin Description
Table 1 summarizes the function of each of the pins available for the component. Only the pins for one master interface are listed. The function of each of the pins of the second master interface is identical – only the pin names change with respect to th
Page: WB_FPU - Accessible Internal Registers
Internal registers within the WB_FPU are not accessed directly. Their content is loaded or accessed by writing to/reading from a particular address (highlighted using a gray background in the block diagram for the peripheral). The following sections summa
Page: WB_FPU - Block Diagram
Figure 1 shows a high-level block diagram for the WB_FPU component. Figure 1. WB_FPU block diagram. For information on the various functional units, see Internal Units. For information on the internal registers for the WB_FPU that can be accessed from the
Page: WB_FPU - Internal Units
The following sections detail the various units that constitute the WB_FPU. Denormalization Units Denormalized numbers themselves are not supported in the WB_FPU. However, for the purposes of calculation, it is necessary to internally perform a light form
Page: WB_FPU - Operational Overview
There is no initialization required for the WB_FPU. As soon as you write an operand value, the calculation and conversion units will be reset – clearing any stored values in the result registers. Example Code The following sections provide example code fo
Page: WB_FPU - Pin Description
The following pin description is for the WB_FPU when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. Table 1. WB_FPU pin description. <table cla
Page: WB_FPU - Wishbone Floating Point Unit
Figure 1. WB_FPU - Wishbone Floating Point Unit. Altium Designer's floating-point unit - WB_FPU - facilitates the conversion of 32-bit integer values into single precision floating-point numbers, and vice-versa. This hardware peripheral performs these con
Page: WB_I2CM - Accessible Internal Registers
The following sections detail the internal registers for the WB_I2CM that can be accessed from the host processor. Control Register (CONTROL) Address: 0h Access: Read/Write Value after Reset: 00h This register is used to control aspects of the Controller'
Page: WB_I2CM - Block Diagram
Figure 1 shows a high-level block diagram for the WB_I2CM component. Figure 1. WB_I2CM block diagram. For information on the internal registers for the WB_I2CM that can be accessed from the host processor, see Accessible Internal Registers.
Page: WB_I2CM - Defining the Frequency of SCLK
The I2C Master Controller incorporates a 16-bit internal register, CLKDIV, whose stored value is used to scale the frequency of the clock signal generated by the Controller – SCLK. This register is further sub-divided into two 8-bit registers accessible b
Page: WB_I2CM - Host to Controller Communications
Communications between a 32-bit host processor and the WB_I2CM are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible intern
Page: WB_I2CM - Operational Overview
After an external reset, the WB_I2CM is effectively ready for use straight away. Initialization After a reset of the WB_I2CM, you may want to initialize the component and set it up ready in accordance with design requirements. Initialization can include:
Page: WB_I2CM - Pin Description
The following pin description is for the WB_I2CM when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be mad
Page: WB_I2CM - Wishbone I2C Master Controller
Figure 1. WB_I2CM - Wishbone I2C Master Controller. The I2C Master Controller component (WB_I2CM) is used to facilitate data transfers over the I2C Bus and therefore ease communication with I2C devices external to the FPGA device. The I2C Bus is a two-wir
Page: WB_I2S - Accessible Internal Registers
The following sections detail the internal registers for the WB_I2S Controller that can be accessed from the host processor. Control Register (CONTROL) Address: 0h Access: Read and Write Value after Reset: 0000_0000h This register is used to store the pre
Page: WB_I2S - Block Diagram
Figure 1 shows a high-level block diagram for the WB_I2S component. Figure 1. WB_I2S block diagram. The block diagram in Figure 1 represents the WB_I2S Controller when configured for operation with both Transmitter and Receiver sections. It also shows use
Page: WB_I2S - Clocks
The prescaler value loaded into the WB_I2S Controller's Control register (CONTROL7..0) is used to set the Sample Rate as follows: Sample Rate = CLK_BASE / (prescaler * 256) The frequency of the WS signal is equal to the Sample Rate. In one cycle of WS, on
Page: WB_I2S - Configurable Wishbone Audio Streaming Controller
Figure 1. WB_I2S - Configurable Wishbone Audio Streaming Controller. The Configurable Audio Streaming Controller component (WB_I2S) is used to facilitate data transfers over the inter-IC sound (I2S) bus. The I2S bus – developed by Philips as a dedicated s
Page: WB_I2S - Configuration
The WB_I2S Controller can be configured after placement on the OpenBus System document, or schematic sheet, using the associated configure dialog (Figure 1). Access to this dialog depends on the document in which you are working: In the OpenBus System doc
Page: WB_I2S - Data Transfer Modes
The following sections detail the available modes of data transfer supported by the WB_I2S Controller. The mode is changed by adjusting the word width, using bits 5..0 of the MODE register.   As a general note, there are some audio devices in the market t
Page: WB_I2S - Host to Controller Communications
Communications between a 32-bit host processor and the WB_I2S Controller are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessi
Page: WB_I2S - Interrupt Generation
The WB_I2S Controller has a single interrupt line (INT_O) that is shared by both the Transmitter and Receiver sections. Interrupt generation is essentially determined by the value defined for watermark, in the Control register (CONTROL31..16). The INT_O s
Page: WB_I2S - Operational Overview
After an external reset, you will need to initialize the WB_I2S Controller. This should be carried out in accordance with design requirements and can include: Loading the required values for the watermark and prescaler to the Control register. Setting the
Page: WB_I2S - Pin Description
The following pin description is for the WB_I2S when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The Controller's external interface signals
Page: WB_I2S - Transmitter and Receiver Reset
The Transmitter section of the Controller can be reset in the following ways: Upon a global reset (RST_I = '1') If the Transmitter Enable bit – txen – in the Mode register (MODE.11) is cleared. After a reset, the valid data in the Transmit FIFO will be cl
Page: WB_IDE - Accessible Internal Registers
The following sections detail the internal registers for the WB_IDE, accessible from the host processor. Data Register (DATA) Address: 00 Access: Read & Write except where indicated as Read-only. Value after Reset: The default value depends on whether the
Page: WB_IDE - Block Diagram
Figure 1 shows a high-level block diagram for the WB_IDE component. Figure 1. WB_IDE block diagram. For information on the internal registers for the WB_IDE that can be accessed from the host processor, see Accessible Internal Registers.
Page: WB_IDE - Host to Controller Communications
Communications between a 32-bit host processor and the WB_IDE Controller are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessi
Page: WB_IDE - Operational Overview
The following sections take a look at initialization of the WB_IDE and example usage. Initialization After an external reset on the RST_I line, you will need to initialize the WB_IDE. This should be carried out in accordance with design requirements and c
Page: WB_IDE - Pin Description
The following pin description is for the WB_IDE when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals to the IDE-c
Page: WB_IDE - Wishbone IDE Interface Controller
Figure 1. WB_IDE - Wishbone IDE Interface Controller. The WB_IDE is a Wishbone-compliant peripheral that provides the control interface between an IDE-compatible storage device, such as a hard disk or Compact Flash memory card, and a processor in the FPGA
Page: WB_INTERCON - Configurable Wishbone Interconnect
Figure 1. WB_INTERCON - Configurable Wishbone Interconnect. The WB_INTERCON peripheral component provides a means of accessing one or more Wishbone-compliant slave devices over a single Wishbone interface. Connecting directly to either the External Memory
Page: WB_INTERCON - Configuration
The WB_INTERCON component can be configured after placement on the schematic sheet. Simply right-click and choose the command to configure the device from the pop-up menu that appears (e.g. Configure U_INTERCON_MEM (WB_INTERCON) for a device with designat
Page: WB_INTERCON - Interfacing
The WB_INTERCON component can be used to connect to one or more slave memory or peripheral I/O devices. The following sections provide examples of where the interconnect component can be used in a design. Connecting Single Slave Devices Although a single
Page: WB_INTERCON - Pin Description
Table 1 summarizes the function of each of the pins available for the WB_INTERCON. Only the pins for one slave interface are listed. The function of each of the pins of subsequently added slave interfaces is identical – only the pin names change with resp
Page: WB_INTERFACE - Concepts
The FPGA-ready Wishbone-compliant components supplied with Altium Designer can be thought of as an extensive set of building blocks. For many 32-bit processor-based designs, these will be sufficient for the design task. However, you may need to implement
Page: WB_INTERFACE - Configuration
The WB_INTERFACE can be configured after placement on the OpenBus System document , or schematic sheet, using the associated Configure (Wishbone Interface) dialog (Figure 1). Access to this dialog depends on the document in which you are working: In the O
Page: WB_INTERFACE - Configuring Item Types
The following sections take a closer look at configuration of each of the supported item types – Internal Register, Command Set, External Address Range – with respect to the WB_INTERFACE's custom interface. Internal Register An internal register allows a
Page: WB_INTERFACE - Custom Wishbone Interface
Figure 1. WB_INTERFACE - Custom Wishbone Interface. The Custom Wishbone Interface component (WB_INTERFACE) enables you to build a custom Wishbone peripheral in a design, extending your 32-bit FPGA systems through the creation of custom FPGA logic. The Cus
Page: WB_INTERFACE - Operational Overview
The following sections take a closer look at the operation of each of the supported item types – Internal Register, Command Set, External Address Range – with respect to the custom interface. Information on the generated C code is also given. Internal Reg
Page: WB_INTERFACE - Pin Description
The following pin description is for the WB_INTERFACE component when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interface. The component's external int
Page: WB_IRRC - Accessible Internal Registers
The following sections detail the internal registers for the WB_IRRC, accessible from the host processor. Clock Divider Register (CLK_DIV) Address: 0h Access: Read and Write Value after Reset: FFFF_FFFFh This register is used to hold a 24-bit value, requi
Page: WB_IRRC - Block Diagram
Figure 1 shows a high-level block diagram for the WB_IRRC component. Figure 1. WB_IRRC block diagram. The function of the WB_IRRC depends on the operational mode defined for the component. Although the block diagram in Figure 1 shows various encoder/decod
Page: WB_IRRC - Host to Controller Communications
Communications between a 32-bit host processor and the WB_IRRC Controller are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the access
Page: WB_IRRC - Interrupts
The WB_IRRC generates a single interrupt flag – rxint – which is reflected in bit 0 of the Status register. The source of the interrupt depends on the current operational mode set for the peripheral: NEC Encoder/Decoder mode (CTRL[7..6] = "01") – the leve
Page: WB_IRRC - Operational Overview
Operation of the WB_IRRC can be broken down into three main areas – initialization, data reception and data transmission. The following sections take a closer look at these areas. Initialization After an external reset (RST_I input goes High), you will ne
Page: WB_IRRC - Pin Description
The following pin description is for the WB_IRRC when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals to the IR T
Page: WB_IRRC - Wishbone Infrared Remote Control Codec
Figure 1. WB_IRRC - Wishbone Infrared Remote Control Codec. The Infrared Remote Control component (WB_IRRC) provides the interface between an infrared transceiver and a processor in an FPGA design. The component has been built primarily to interface to th
Page: WB_JPGDEC_V2 - Accessible Internal Registers
The following sections detail the internal registers for the WB_JPGDEC_V2 that can be accessed from the host processor. Status Register (STATUS) Address: 0h Access: Read only except where indicated Value after Reset: 0000_0100h This register reflects the
Page: WB_JPGDEC_V2 - Block Diagram
Figure 1 shows a high-level block diagram for the WB_JPGDEC_V2 component. Figure 1. WB_JPGDEC_V2 block diagram. For information on the internal registers for the WB_JPGDEC_V2 that can be accessed from the host processor, see Accessible Internal Registers.
Page: WB_JPGDEC_V2 - Host to Controller Communications
Communications between a 32-bit host processor and the WB_JPGDEC_V2 are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible i
Page: WB_JPGDEC_V2 - Interrupts
The WB_JPGDEC_V2 provides for a single external interrupt line to the host processor. This line – INT_O – will be taken High if any of the following readable bits in the Status register become set: jpgrdy (STATUS.0) rempty (STATUS.1) wfull (STATUS.2) jpge
Page: WB_JPGDEC_V2 - Operational Overview
The following sections take a look at initialization of the WB_JPGDEC_V2 and example usage. Initialization After an external reset on the RST_I line, you will need to initialize the WB_JPGDEC_V2. This should be carried out in accordance with design requir
Page: WB_JPGDEC_V2 - Pin Description
The following pin description is for the WB_JPGDEC_V2 when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. Table 1. WB_JPGDEC_V2 pin description
Page: WB_JPGDEC_V2 - Wishbone JPEG Decoder (Version 2)
Figure 1. WB_JPGDEC_V2 - Wishbone JPEG Decoder (Version 2). The Wishbone JPEG Decoder component (WB_JPGDEC_V2) facilitates the decoding of baseline JPEG-compressed images (grayscale and color) into RGB565 pixel format output that can be written directly t
Page: WB_LCDCTRL - Block Diagram
Figure 1 shows a high-level block diagram for the WB_LCDCTRL component. Figure 1. WB_LCDCTRL block diagram. For details of the operation of the FSM, see Operational Overview.
Page: WB_LCDCTRL - Host to Controller Communications
The following sections detail the standard handshaking that takes place when the host processor communicates with the WB_LCDCTRL over the Wishbone interface. Writing Data to the WB_LCDCTRL Data is written from the host processor (Wishbone Master) to the W
Page: WB_LCDCTRL - Operational Overview
The LCD Controller is implemented as a Finite State Machine, with a maximum operating frequency of 50 MHz. The Cycle Counter is an internal 7-bit counter used to control transitions between certain states of the FSM. Internally, the ADR_I input is connect
Page: WB_LCDCTRL - Pin Description
The following pin description is for the WB_LCDCTRL when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be
Page: WB_LCDCTRL - Wishbone LCD Controller
Figure 1. WB_LCDCTRL - Wishbone LCD Controller. The LCD Controller component (WB_LCDCTRL) provides an interface between a host processor and an LCD panel that is equipped with a KS0066U-compatible Controller. The Controller enables you to communicate dire
Page: WB_LCDCTRL_SRAM - Block Diagram
Figure 1 shows a high-level block diagram for the WB_LCDCTRL_SRAM component. Figure 1. WB_LCDCTRL_SRAM block diagram. For details of the operation of the FSM, see Operational Overview.
Page: WB_LCDCTRL_SRAM - Host to Controller Communications
The following sections detail the standard handshaking that takes place when the host processor communicates with the WB_LCDCTRL_SRAM over the Wishbone interface, with a view to writing data to/reading data from the LCD panel. Writing Data to the WB_LCDCT
Page: WB_LCDCTRL_SRAM - Operational Overview
The LCD Controller is implemented as a Finite State Machine, with a maximum operating frequency of 50 MHz. The Cycle Counter is an internal 7-bit counter used to control transitions between certain states of the FSM. The Internal Multiplexing is used to c
Page: WB_LCDCTRL_SRAM - Pin Description
The following pin description is for the WB_LCDCTRL_SRAM when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals wil
Page: WB_LCDCTRL_SRAM - Wishbone LCD Controller with Multiplexed Access to SRAM
Figure 1. WB_LCDCTRL_SRAM - Wishbone LCD Controller, offering additional multiplexed access to SRAM. The LCD Controller component (WB_LCDCTRL_SRAM) provides an interface between a host processor and an LCD panel that is equipped with a KS0066U-compatible
Page: WB_MEM_CTRL - Configurable Wishbone Memory Controller
Figure 1. WB_MEM_CTRL - Configurable Wishbone Memory Controller (Example SRAM Configuration shown). The Memory Controller component (WB_MEM_CTRL) provides a simple, configurable interface, between a 32-bit processor and either single data rate Synchronous
Page: WB_MEM_CTRL - Configuration
The Memory Controller can be configured after placement on the OpenBus System document, or schematic sheet, using the associated configure dialog (Figure 1). Access to this dialog depends on the document in which you are working: In the OpenBus System doc
Page: WB_MEM_CTRL - Interfacing
For 32-bit processors the physical interface to the outside world is always 32 bits wide. Since the addressing has a byte-level resolution, this means that up to four "packets" of data (bytes) can be loaded or stored during a single memory access. To acco
Page: WB_MEM_CTRL - Pin Description (BRAM-Configured)
Figure 1. WB_MEM_CTRL configured as a BRAM Controller. The schematic symbol shown in Figure 1 represents the Memory Controller when configured to connect to physical Block RAM that is 1KB (256 x 32-bit) in size. Depending on the size of RAM that you speci
Page: WB_MEM_CTRL - Pin Description (Flash-Configured)
Figure 1. WB_MEM_CTRL configured as a Flash Controller. The schematic symbol shown in Figure 1 represents the Memory Controller when configured to connect to a single, 32-bit wide physical Parallel Flash memory device that is 1KB (256 x 32-bit) in size. M
Page: WB_MEM_CTRL - Pin Description (SDRAM-Configured)
Figure 1. WB_MEM_CTRL configured as an SDRAM Controller. The schematic symbol shown in Figure 1 represents the Memory Controller when configured to connect to a single, 32-bit wide physical SDRAM device that is 8MB (2M x 32-bit) in size. Memory layout and
Page: WB_MEM_CTRL - Pin Description (SRAM-Configured)
Figure 1. WB_MEM_CTRL configured as an SRAM Controller. The schematic symbol shown in Figure 1 represents the Memory Controller when configured to connect to 2, 16-bit wide physical SRAM devices, with a size of 1MB (256K x 32-bit). Memory layout and size
Page: WB_MEM_CTRL Configuration - Asynchronous SRAM Settings
When the chosen memory type is Asynchronous SRAM, the Configure (Memory Controller) dialog will appear as shown in Figure 1. Figure 1. Configuration options when interfacing to SRAM. The following sections detail each of the configuration options availabl
Page: WB_MEM_CTRL Configuration - Block RAM Settings
When the chosen memory type is Block RAM, the Configure (Memory Controller) dialog will appear as shown in Figure 1. Figure 1. Configuration options when interfacing to BRAM. The following sections detail each of the configuration options available. Size
Page: WB_MEM_CTRL Configuration - Parallel Flash Settings
When the chosen memory type is Parallel FLASH, the Configure (Memory Controller) dialog will appear as shown in Figure 1. Figure 1. Configuration options when interfacing to Flash memory. The following sections detail each of the configuration options ava
Page: WB_MEM_CTRL Configuration - Synchronous DRAM Settings
When the chosen memory type is Synchronous DRAM, the Configure (Memory Controller) dialog will appear as shown in Figure 1. Figure 1. Configuration options when interfacing to SDRAM. The following sections detail each of the configuration options availabl
Page: WB_MP3DEC - Accessible Internal Registers
The following sections detail the internal registers for the WB_MP3DEC that can be accessed from the host processor. Status and Control Register (STATUS) Address: 0h Access: Read/Write Size: 5 bits Reset value: 3 Bit Access Name Function 0 Write Start Wri
Page: WB_MP3DEC - Wishbone MP3 Decoder
Japanese Parent article: Wishbone Components WB_MP3DEC - Wishbone MP3 Decoder. The Wishbone MP3 Decoder component (WB_MP3DEC) facilitates the decoding of MPEG-2 Layer 3 encoded audio data ('MP3') into dual-channel 16-bit signed samples. The WB_MP3DEC feat
Page: WB_MULTIMASTER - Configurable Wishbone Multi-Master
Figure 1. WB_MULTIMASTER - Configurable Wishbone Multi-Master. The WB_MULTIMASTER peripheral component provides a simple means of sharing a slave Wishbone device between multiple masters. Similar to, and essentially and extension of the Wishbone Dual Mast
Page: WB_MULTIMASTER - Configuration
The WB_MULTIMASTER component can be configured after placement on the schematic sheet. Simply right-click and choose the command to configure the component from the pop-up menu that appears (e.g. Configure U_MM1 (WB_MULTIMASTER) for a component with desig
Page: WB_MULTIMASTER - Interfacing
Figure 1 shows an example of using a configurable Wishbone Multi-Master to share access to the same physical SRAM between one 32-bit processor (a Nios II) and, although not shown, two memory-based peripheral devices (a BT656 Video Capture Controller and a
Page: WB_MULTIMASTER - Pin Description
Table 1 summarizes the function of each of the pins available for the component. Only the pins for one master interface are listed. The function of each of the pins of the additional master interfaces is identical – only the pin names change with respect
Page: WB_OWM - Accessible Internal Registers
The following sections detail the internal registers for the WB_OWM that can be accessed from the host processor. Command Register (CMD) Address: 0h Access: Read and Write Value after Reset: 00h This register is used to set the operational mode of the WB_
Page: WB_OWM - Block Diagram
Figure 1 shows a high-level block diagram for the WB_OWM component. Figure 1. WB_OWM block diagram. For information on the internal registers for the WB_OWM that can be accessed from the host processor, see Accessible Internal Registers.
Page: WB_OWM - Host to Controller Communications
Communications between a 32-bit host processor and the WB_OWM are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible interna
Page: WB_OWM - Operational Overview
The following sections summarize initialization of the WB_OWM Controller, detection of slave devices on the 1-Wire bus, and sending and receiving of data over the bus. Initialization After an external reset, you will need to initialize the WB_OWM. This sh
Page: WB_OWM - Pin Description
The following pin description is for the device when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The Controller's external interface signals
Page: WB_OWM - Wishbone 1-Wire Master Controller
Figure 1. WB_OWM - Wishbone 1-Wire Master Controller. The WB_OWM is a 1-Wire® Master Controller that facilitates communications between an FPGA-based processor and external 1-Wire-compatible peripheral devices, over the 1-Wire serial bus. The Controller h
Page: WB_PRTIO - Block Diagrams
The following sections provide high-level block diagrams for each of the three port types to which the WB_PRTIO component can be configured – Output, Input/Output and Tristate. Port Type: Output Figure 1. Block Diagram for WB_PRTIO configured as port type
Page: WB_PRTIO - Configurable Wishbone Parallel Port Unit
Figure 1. WB_PRTIO - Configurable Wishbone Parallel Port Unit. The WB_PRTIO is a Wishbone-compliant, configurable parallel port unit, providing a simple register interface for storing data to be transferred to/from another device in a design. For example,
Page: WB_PRTIO - Configurable Wishbone Parallel Port Unit (AD10)
Japanese Altium Designer 10 delivers an enhanced configurable Wishbone Parallel Port Unit (WB_PRTIO), configuration of which is far more powerful and intuitive. No longer are you constrained to having a peripheral configurable to 1, 2 or 4 ports only. Now
Page: WB_PRTIO - Configuration
The Port IO component can be configured after placement on the OpenBus System document, or schematic sheet, using the associated configuration dialog (Figure 1). Access to this dialog depends on the document in which you are working: In the OpenBus System
Page: WB_PRTIO - Host to Controller Communications
Communications between the host peripheral (e.g. processor) and the WB_PRTIO component is carried out over the standard Wishbone bus. The host peripheral device can write to/read from any of the WB_PRTIO's internal registers. Selection of a particular reg
Page: WB_PRTIO - Pin Description
The following pin description is for the WB_PRTIO when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be ma
Page: WB_PRTIO - Register Reset Values
Table 1 shows the values contained in each of the WB_PRTIO's internal registers after an external system reset has been received on the RST_I input. Table 1. WB_PRTIO Register reset values. <table class='confluenceTable'><tbody> <tr> <th class='confluence
Page: WB_PWM8 - Accessible Internal Registers
The following sections detail the internal registers for the WB_PWM8 that can be accessed from the host processor. Pulse Width Register (PWMRG) Address: 0h Access: Read/Write Value after Reset: 00h This register holds the value (00h to FFh) of the desired
Page: WB_PWM8 - Block Diagram
Figure 1 shows a high-level block diagram for the WB_PWM8 component. Figure 1. WB_PWM8 block diagram. The core is fully synchronous, with both counters and the comparator clocked using the external system clock signal (CLK_I). After a reset, the 8-bit PWM
Page: WB_PWM8 - Generated Output Frequency
The frequency of the pulse-width-modulated rectangular wave output signal, when enabled, is given by:
Page: WB_PWM8 - Initialization
The following steps outline the basic procedure to initialize the WB_PWM8 Controller ready for operation. You will need to re-initialize the Controller after each external reset. Write the required value for the pulse width to the PWMRG register Write the
Page: WB_PWM8 - Pin Description
The following pin description is for the WB_PWM8 when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The Controller's external interface signal
Page: WB_PWM8 - Wishbone Standard Pulse Width Modulation Controller
Figure 1. WB_PWM8 - Wishbone Standard Pulse Width Modulation Controller. The Standard Pulse Width Modulation Controller component (WB_PWM8) is capable of generating PWM counter and/or Pre-scaler counter interrupts and a differential pulse-width-modulated
Page: WB_PWM8, WB_PWMX - Interrupts
After a counter overflow event occurs, the INT_O pin will be asserted after one cycle of the external clock signal (CLK_I). This will only occur provided that: the global interrupt enable bit (pien) is set High in the Control register (PWCON.1) and the re
Page: WB_PWMX - Accessible Internal Registers
The following sections detail the internal registers for the WB_PWMX that can be accessed from the host processor. Pulse Width Register (PWMRG) Address: 0h – PWMRGLO, 4h – PWMRGHI Access: Read/Write Value after Reset: 00_0000_0000_0000b The 14-bit PWMRG r
Page: WB_PWMX - Block Diagram
Figure 1 shows a high-level block diagram for the WB_PWMX component. Figure 1. WB_PWMX block diagram. The core is fully synchronous, with both counters and the comparator clocked using the external system clock signal (CLK_I). The resolution of the PWM Co
Page: WB_PWMX - Generated Output Frequency
The frequency of the pulse-width-modulated rectangular wave output signal, when enabled, is given by: where Res is the current resolution mode (mod1:mod) represented in decimal format. Therefore: for 8-bit resolution, Res = 0 for 10-bit resolution, Res =
Page: WB_PWMX - Host to Controller Communications
Communications between a 32-bit host processor and the WB_PWMX Controller are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the access
Page: WB_PWMX - Initialization
The following steps outline the basic procedure to initialize the WB_PWMX Controller ready for operation. You will need to re-initialize the Controller after each external reset. Write the resolution control bits (mod1 and mod0) in the Control register (P
Page: WB_PWMX - Pin Description
The following pin description is for the WB_PWMX when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The Controller's external interface signal
Page: WB_PWMX - Wishbone Extended Pulse Width Modulation Controller
Figure 1. WB_PWMX - Wishbone Extended Pulse Width Modulation Controller. The Extended Pulse Width Modulation Controller component (WB_PWMX) is capable of generating PWM counter and/or Pre-scaler counter interrupts and a differential pulse-width-modulated
Page: WB_SDCARD - Accessible Internal Registers
The following sections detail the internal registers for the WB_SDCARD that can be accessed from the host processor. Data Register for 8-bit Transfers (DATA8) Address: 000 Access: Read/Write Value after Reset: Undetermined This is not actually a register
Page: WB_SDCARD - Block Diagram
Figure 1 shows a high-level block diagram for the WB_SDCARD component. Figure 1. WB_SDCARD block diagram. For information on the internal registers for the WB_SDCARD that can be accessed from the host processor, see Accessible Internal Registers.
Page: WB_SDCARD - Host to Controller Communications
Communications between a 32-bit host processor and the WB_SDCARD are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible inte
Page: WB_SDCARD - Operational Overview
The following steps outline the basic procedure in order to initiate serial communications with the target SD Card. Initialization You will need to re-initialize the Controller after each external reset. This should be carried out in accordance with desig
Page: WB_SDCARD - Pin Description
The following pin description is for the WB_SDCARD component when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals
Page: WB_SDCARD - Wishbone SD Card Controller
Figure 1. WB_SDCARD - Wishbone SD Card Controller. The Wishbone SD Card Controller component (WB_SDCARD) provides an SPI Master interface, enabling a host processor to efficiently communicate with a Secure Digital (SD) storage device – resident outside of
Page: WB_SDHC - Accessible Internal Registers
The following sections detail the internal registers for the SDHC Controller that can be accessed from the host processor. Clock Divider Register (CDIV) Address: 00h Access: Read/Write Size: 10 bits Reset value: 0 This 10-bit register divides the system c
Page: WB_SDHC - Wishbone SDHC Controller
Japanese Parent article: Wishbone Components WB_SDHC - Wishbone SDHC Controller. The Wishbone SDHC Controller component (WB_SDHC) provides an interface that enables a host processor to efficiently communicate with a Secure Digital (SD) or Secure Digital H
Page: WB_SHARED_MEM_CTRL - Configurable Wishbone Shared Memory Controller
Figure 1. WB_SHARED_MEM_CTRL - Configurable Wishbone Shared Memory Controller. The Shared Memory Controller component (WB_SHARED_MEM_CTRL) provides an interface between a 32-bit processor and memories on a shared bus. The Controller provides access to, an
Page: WB_SHARED_MEM_CTRL - Configuration
The Shared Memory Controller can be configured after placement on the OpenBus System document, or schematic sheet, using the associated configure dialog (Figure 1). Access to this dialog depends on the document in which you are working: In the OpenBus Sys
Page: WB_SHARED_MEM_CTRL - Interfacing
Physical memory is connected to a processor's External Memory interface. How the WB_SHARED_MEM_CTRL is placed and wired within an FPGA design to facilitate this, depends on the method used to build that design. The main processor-based system can be defin
Page: WB_SHARED_MEM_CTRL - Pin Description
The following pin description is for the WB_SHARED_MEM_CTRL when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The interface signals to physic
Page: WB_SHARED_MEM_CTRL Configuration - Asynchronous SRAM Settings
Clicking on the Asynchronous SRAM entry in the left-hand pane of the Configure Memory Controller dialog will open the Asynchronous SRAM page, as shown in Figure 1. Figure 1. Configuration options when interfacing to asynchronous SRAM. The following sectio
Page: WB_SHARED_MEM_CTRL Configuration - General Settings
Figure 1. General settings for the Shared Memory Controller. The General page of the Configure Memory Controller dialog provides options for configuring the graphical nature of the component, as well as clock synchronization when interfacing to SDRAM. The
Page: WB_SHARED_MEM_CTRL Configuration - Parallel Flash Settings
Clicking on the Parallel Flash entry in the left-hand pane of the Configure Memory Controller dialog will open the Parallel Flash page, as shown in Figure 1. Figure 1. Configuration options when interfacing to parallel Flash memory. The following sections
Page: WB_SHARED_MEM_CTRL Configuration - Synchronous DRAM Settings
Clicking on the Synchronous DRAM entry in the left-hand pane of the Configure Memory Controller dialog will open the Synchronous DRAM page, as shown in Figure 1. Figure 1. Configuration options when interfacing to Synchronous DRAM. The following sections
Page: WB_SPI - Accessible Internal Registers
The following sections detail the internal registers for the WB_SPI that can be accessed from the host processor. Data Register for 8-bit Transfers (DATA8) Address: 000 Access: Read/Write Value after Reset: Undetermined This is not actually a register in
Page: WB_SPI - Block Diagram
Figure 1 shows a high-level block diagram for the WB_SPI component. Figure 1. WB_SPI block diagram. For information on the internal registers for the WB_SPI that can be accessed from the host processor, see Accessible Internal Registers.
Page: WB_SPI - Host to Controller Communications
Communications between a 32-bit host processor and the WB_SPI are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible interna
Page: WB_SPI - Operational Overview
The following steps outline the basic procedure in order to initiate serial communications with the target SPI peripheral device. Initialization You will need to re-initialize the Controller after each external reset. This should be carried out in accorda
Page: WB_SPI - Pin Description
The following pin description is for the WB_SPI component when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals wi
Page: WB_SPI - Wishbone Serial Peripheral Interface Controller
Figure 1. WB_SPI - Wishbone Serial Peripheral Interface Controller. The Wishbone Serial Peripheral Interface Controller component (WB_SPI) provides an SPI Master interface, enabling a host processor to efficiently communicate with a slave SPI peripheral d
Page: WB_TSPENDOWN - Operational Overview
Operation of the WB_TSPENDOWN is very simple and straightforward. Simply perform a Wishbone Read of the component and poll bit 0 of the 8-bit data word sent out on the component's DAT_O line. Bits 7..1 of this data are fixed as '0's. When DAT_O(0) is '0',
Page: WB_TSPENDOWN - Pin Description
The following pin description is for the WB_TSPENDOWN when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The Controller's external interface s
Page: WB_TSPENDOWN - Wishbone Touch Screen Pen Controller
Figure 1. WB_TSPENDOWN - Wishbone Touch Screen Pen Controller. The TFT LCD panel on the Desktop NanoBoard features an analog resistive touch screen. Control for the touch screen is provided through an AD7843ARU Touch Screen Digitizer (from Analog Devices)
Page: WB_UART8_V2 - Accessible Internal Registers
The following sections detail the internal registers for the WB_UART8_V2 that can be accessed from the host processor. Baud Rate Generator Register (BRG) Address: BRG[23..16] – 0000, BRG[15..8] – 0001, BRG[7..0] – 0010 Access: Read/Write Value after Reset
Page: WB_UART8_V2 - Block Diagram
Figure 1 shows a high-level block diagram for the WB_UART8_V2 component. Figure 1. WB_UART8_V2 block diagram. For information on the internal registers for the WB_UART8_V2 that can be accessed from the host processor, see Accessible Internal Registers.
Page: WB_UART8_V2 - Host to Controller Communications
Communications between a 32-bit host processor and the WB_UART8_V2 are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible in
Page: WB_UART8_V2 - Operational Overview
After an external reset, the WB_UART8_V2 is effectively ready for use straight away. The hardware controlled handshaking is disabled after a reset – meaning that if data is available in the Transmit Buffer, the device will start sending it, regardless of
Page: WB_UART8_V2 - Pin Description
The following pin description is for the WB_UART8_V2 when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be
Page: WB_UART8_V2 - Wishbone Serial Communications Port (AD10)
Japanese Parent article: Wishbone Components The WB_UART8_V2 peripheral has been enhanced in Altium Designer 10. It now provides the following new features over its predecessor: Word length can be set to 5, 6, 7, or 8 bits Parity can be set to None, Odd,
Page: WB_UART8_V2 - Wishbone Serial Communications Port (Version 2)
Figure 1. WB_UART8_V2 - Wishbone Serial Communications Port (Version 2). Serial ports on embedded systems often provide a 2-wire communication channel only. The Wishbone Serial Communications Port component (WB_UART8_V2) facilitates serial communication w
Page: WB_USB - Accessible Internal Registers
The following sections detail the internal registers for the WB_USB that can be accessed from the host processor. Reset Cycles Register (RESET_CYC) Address: 10000 Access: Write Value after Reset: 00011111 This register is used to store the value for the n
Page: WB_USB - Block Diagram
Figure 1 shows a high-level block diagram for the WB_USB component. Figure 1. WB_USB block diagram. For information on the internal registers for the WB_USB that can be accessed from the host processor, see Accessible Internal Registers.
Page: WB_USB - Configurable Wishbone Universal Serial Bus Interface Controller
Figure 1. WB_USB - Configurable Wishbone Universal Serial Bus Interface Controller. The WB_USB peripheral provides the interface between a processor in the FPGA design and an external USB Interface device, for subsequent communications over a Universal Se
Page: WB_USB - Configuration
The WB_USB Controller can be configured after placement on the OpenBus System document, or schematic sheet, using the associated configure dialog (Figure 1). Access to this dialog depends on the document in which you are working: In the OpenBus System doc
Page: WB_USB - Host to Controller Communications
Communications between a 32-bit host processor and the WB_USB are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to the accessible internal registers,
Page: WB_USB - Operational Overview
With respect to the WB_USB Controller itself, provided you have configured the width of the USB_D line as required, you really only need to load values for the various cycle times, after an external reset, in accordance with design requirements. If the de
Page: WB_USB - Pin Description
The following pin description is for the WB_USB when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The Controller's external interface signals
Page: WB_VGA - Configurable Wishbone Display Driver
Figure 1. WB_VGA - Configurable Wishbone Display Driver. The Wishbone Display Driver (WB_VGA) is a configurable component that can be setup to operate as any of the three 32-bit VGA Controllers available in Altium Designer, and summarized as follows: VGA3
Page: WB_VGA - Configuration
The WB_VGA component can be configured after placement on the schematic sheet. Simply right-click and choose the Configure command from the pop-up menu that appears. Alternatively, click on the Configure button, available in the Component Properties dialo
Page: What fields and columns can be used in an Excel Bill of Materials template?
When creating a Bill of Materials template in Excel, a combination of Fields and Columns may be used to specify the desired layout. Several example templates are provided with Altium Designer, in the Templates folder of the main installation. A full list
Page: What is the Altium Designer RTL
The Altium Designer Run Time Library (RTL) is composed of Application Programming Interfaces (APIs). Many editors in Altium Designer have their own APIs. For example the PCB editor has the PCB API, Schematic editor has the Schematic API, the Project Manag
Page: What's New in Altium Designer
Altium Designer 新功能介绍 Altium Designer の新機能  Release Notes for Altium Designer Complete list of Altium Designer 2013 updates Complete list of Altium Designer 10/12 updates Altium Designer mini-site AltiumLive Altium Videos Design Secrets Each update to Alt
Page: Whats New in Altium Designer 6.0
{excerpt} Altium Designer 6.0 brings a host of new and enhanced features to improve PCB and FPGA design productivity. This release includes a mix of major new features and technologies, combined with numerous smaller enhancements. Many of the enhancements
Page: Whats New in Altium Designer 6.3
{excerpt} Continuing to improve productivity, the release of Altium Designer 6.3 brings a new PCB graphics engine, offering substantial drawing speed improvements. Numerous other new and enhanced features help make Altium Designer an even more productive
Page: Whats New in Altium Designer 6.6
{excerpt} Altium Designer 6.6 brings significant refinements to Variants combined with a number of smaller enhancements and improved system-wide support for existing technologies. Many of these improvements are based on feedback directly from you, the eng
Page: Whats New in Altium Designer 6.7
{excerpt} Altium Designer 6.7 continues to improve your productivity delivering features for high-speed design such as Interactive Length Tuning and PCB Layer Tabs. New library tools and a variety of new capabilities strengthen Altium Designer as a unifie
Page: Whats New in Altium Designer 6.8
{excerpt} Continuing to improve your productivity, Altium Designer 6.8 brings a new DxDesigner Importer as well as Interactive Length Tuning for Differential Pairs. Numerous other new and enhanced features facilitate making your design process more effect
Page: Whats New in Altium Designer 6.9
{excerpt} Altium Designer 6.9 brings significant refinements to 3D PCB Visualization combined with a number of smaller enhancements and improved system-wide support for existing technologies. Many of these improvements are based on feedback directly from
Page: Whats New in Altium Designer Summer 08
Summer 08 Highlights Altium Designer Summer 08 brings significant new and enhanced features to unify the design process, make project management easier, expand access to FPGAs and improve design productivity - helping you create a return on your innovatio
Page: Which Objects/Features are supported by the collaborative PCB Design Feature?
When working in Collaborative PCB Design, some objects/features are not supported by the merge process. This is a summary of the objects that are supported or not. Supported: Tracks Arcs Fills Solid Regions Pads Vias (also Blind & Buried) Dimensions Coord
Page: Why can't I get all schematic pages to print?
Make sure that all sheets have unique page numbers. Use the feature Number schematic sheets from the menu: Tools>>Number Schematic Sheets
Page: Why do I get the error "The Film is too small for this PCB" when generating Gerber files?
This error appears when the primitives in the PCB document do not fit into the area specified by in the Gerber export settings. This may be because the board/panel is too big for that area, or because there are off-board objects that are making the extent
Page: Why is my polygon clearance rule ignored?
Clearance rules for polygons must use the InPolygon, InPoly or InNamedPolygon keyword as opposed to IsPolygon. Polygon Pours should be thought of as containers for either Region or Track objects, which are regenerated as needed when the polygon pour is re
Page: Width
Defines the width of tracks placed on the copper (signal) layers. Creating Design Rules Design Rules   Constraints Min Width   specifies the minimum permissible width to be used for tracks when routing the board. Specifying a value here will apply to all
Page: Wiring up an OpenBus System
You've placed the required devices in your system, now it's time to wire up those devices. In the schematic world, wiring between devices requires individual placement of wires and buses between corresponding pins of each signal in the interface. In some
Page: Wishbone Communications
The following sections detail the standard handshaking that takes place when a 32-bit processor communicates to a slave peripheral or memory device connected to the relevant Wishbone interface port. Both of the processor's Wishbone ports can be configured
Page: Wishbone Communications - 32-bit Processor to Slave Peripheral
Communications between a 32-bit host processor and a slave IO peripheral component are carried out over a standard Wishbone bus interface. The following sections detail the communication cycles involved between Host and Controller for writing to/reading f
Page: Wishbone Components
What do I need to know about Wishbone? Altium Designer offers a range of peripheral components for use in your designs, that utilize the Wishbone bus standard. This standard is formally described as a "System-on-Chip Interconnection Architecture for Porta
Page: Wishbone Interface Background
To normalize access to hardware and peripherals, each of the 32-bit processors supported in Altium Designer has a Wishbone-based FPGA core that 'wraps' around the processor. This enables peripherals defined in the FPGA to be used transparently with any ty
Page: Wishbone Probe Instrument
The Summer 09 release of Altium Designer sees the introduction of a new Wishbone Probe instrument (WB_PROBE). This instrument is a Wishbone Master that essentially allows you to tap into a Wishbone bus and 'probe' any of the Wishbone-compliant slave devic
Page: Working with Altera Devices and Place and Route Tools
Altium Designer's FPGA development environment can be used to capture, synthesize, place and route and download a digital system design into an FPGA. Place and route, the process of implementing the design on the target silicon, requires an intimate under
Page: Working with Documents
Japanese In Altium Designer, each type of document is opened and edited in an associated editor. For example, a schematic document is opened and edited in the Schematic Editor, a PCB library document in the PCB Library Editor, and so on. As you create a n
Page: Working with Panels
Workspace panels are essential elements of the Altium Designer environment. Whether specific to a particular document editor or used on a more global, system-wide level, they present information and controls that aid productivity and allow you to design m
Page: Working with the Board Insight System
Board Insight™ is a configurable system of features that give you complete control over viewing and working with your PCB design. A complex multi-layer board makes for a visually dense and often difficult to interpret workspace. Altium Designer's Board In
Page: Working with the Query System
The Query System in Altium Designer's schematic and PCB editors allow you to write queries to filter down to find and edit precisely those design objects you require. An Insiders Guide to the Query Language Introduction to the Query Language Query Languag
Page: Working with the Sim Data Editor
This application note provides detailed information on displaying and managing waveforms, created as a result of performing simulation or signal integrity analysis of your circuit design. Whether you run a mixed-signal simulation on a circuit, or a pre-/p
Page: Working with Version-Controlled Database Libraries
Version-Controlled Database Library で作業   This document provides detailed information on placing components from a database using Altium Designer's SVN Database Library feature. The ability to place components directly from a database using a Database Lib
Page: Working with Xilinx Devices and Place and Route Tools
Altium Designer's FPGA development environment can be used to capture, synthesize, place and route and download a digital system design into an FPGA. Place and route, the process of implementing the design on the target silicon, requires an intimate under
Page: WorkSpace Manager Processes
This section covers the Work Space Manager processes and their parameters (if any). ClipBoardAction process Description Execute a specified action for the clipboard, to cut, copy, paste or clear the contents from the Workspace manager clipboard. For examp

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Page: XC3S1400AN-4FGG676C - Feature Summary
Figure 1. Xilinx Spartan-3AN FPGA<br>(XC3S1400AN-4FGG676C). The XC3S1400AN-4FGG676C device is a member of the Spartan-3AN family of FPGAs. The Spartan-3AN provides a low-cost, high-density solution for applications such as those targeted to the consumer e
Page: XC3S1400AN-4FGG676C - Supported Differential IO Standards
The following table lists the differential I/O standards supported by the XC3S1400AN-4FGG676C device. Table 1. Supported differential I/O standards. <DIV align="center"><b>I/O Standard</b></DIV> <DIV align="center"><b>Description</b></DIV> BLVDS_25 Bus Lo
Page: XC3S1400AN-4FGG676C - Supported Single-Ended IO Standards
The following table lists the single-ended I/O standards supported by the XC3S1400AN-4FGG676C device. Table 1. Supported single-ended I/O standards. <DIV align="center"><b>I/O Standard</b></DIV> <DIV align="center"><b>Description</b></DIV> HSTL_I High-Spe
Page: XC3S1500-4FG676C - Feature Summary
Figure 1. Xilinx Spartan-3 FPGA<br>(XC3S1500-4FG676C). The XC3S1500-4FG676C device is a member of the 1.2V Spartan-3 family of FPGAs. The Spartan-3 provides a low-cost, high-density solution for applications such as those targeted to the consumer electron
Page: XC3S1500-4FG676C - Supported Differential IO Standards
The following table lists the differential I/O standards supported by the XC3S1500-4FG676C device. Table 1. Supported differential I/O standards. <DIV align="center"><b>I/O Standard</b></DIV> <DIV align="center"><b>Description</b></DIV> BLVDS_25 Bus Low-V
Page: XC3S1500-4FG676C - Supported Single-Ended IO Standards
The following table lists the single-ended I/O standards supported by the XC3S1500-4FG676C device. Table 1. Supported single-ended I/O standards. <DIV align="center"><b>I/O Standard</b></DIV> <DIV align="center"><b>Description</b></DIV> GTL Gunning Transc
Page: XC3SD1800A-4FGG676C - Feature Summary
Figure 1. Xilinx Spartan-3A DSP FPGA<br>(XC3SD1800A-4FGG676C). The XC3SD1800A-4FGG676C device is a member of the Spartan-3A DSP family of FPGAs. The Spartan-3A DSP provides a low-cost, high-performance DSP solution for high-volume, cost-critical applicati
Page: XC3SD1800A-4FGG676C - Supported Differential IO Standards
The following table lists the differential I/O standards supported by the XC3SD1800A-4FGG676C device. Table 1. Supported differential I/O standards. <DIV align="center"><b>I/O Standard</b></DIV> <DIV align="center"><b>Description</b></DIV> BLVDS_25 Bus Lo
Page: XC3SD1800A-4FGG676C - Supported Single-Ended IO Standards
The following table lists the single-ended I/O standards supported by the XC3SD1800A-4FGG676C device. Table 1. Supported single-ended I/O standards. <DIV align="center"><b>I/O Standard</b></DIV> <DIV align="center"><b>Description</b></DIV> HSTL_I High-Spe
Page: XC4VLX25-10FF668C - Feature Summary
Figure 1. Xilinx Virtex-4 FPGA<br>(XC4VLX25-10FF668C). The XC4VLX25-10FF668C device is a member of the Virtex-4 family of FPGAs. The Virtex-4 family is comprised of 17 devices in total, over three platform families – LX, SX and FX. The LX series, of which
Page: XC4VLX25-10FF668C - Supported Differential DCI IO Standards
The following table lists the differential DCI (Digitally Controlled Impedance) I/O standards supported by the XC4VLX25-10FF668C device. Table 1. Supported differential DCI I/O standards. <DIV align="center"><b>I/O Standard</b></DIV> <DIV align="center"><
Page: XC4VLX25-10FF668C - Supported Differential IO Standards
The following table lists the differential I/O standards supported by the XC4VLX25-10FF668C device. Table 1. Supported differential I/O standards. <DIV align="center"><b>I/O Standard</b></DIV> <DIV align="center"><b>Description</b></DIV> BLVDS_25 Bus Low-
Page: XC4VLX25-10FF668C - Supported Single-Ended DCI IO Standards
The following table lists the single-ended DCI (Digitally Controlled Impedance) I/O standards supported by the XC4VLX25-10FF668C device. Table 1. Supported single-ended DCI I/O standards. <DIV align="center"><b>I/O Standard</b></DIV> <DIV align="center"><
Page: XC4VLX25-10FF668C - Supported Single-Ended IO Standards
The following table lists the single-ended I/O standards supported by the XC4VLX25-10FF668C device. Table 1. Supported single-ended I/O standards. <DIV align="center"><b>I/O Standard</b></DIV> <DIV align="center"><b>Description</b></DIV> GTL Gunning Trans
Page: XC4VSX35-10FFG668C - Feature Summary
Figure 1. Xilinx Virtex-4 FPGA<br>(XC4VSX35-10FFG668C). The XC4VSX35-10FFG668C device is a member of the Virtex-4 family of FPGAs. The Virtex-4 family is comprised of 17 devices in total, over three platform families – LX, SX and FX. The SX series, of whi
Page: XC4VSX35-10FFG668C - Supported Differential DCI IO Standards
The following table lists the differential DCI (Digitally Controlled Impedance) I/O standards supported by the XC4VSX35-10FFG668C device. Table 1. Supported differential DCI I/O standards. <DIV align="center"><b>I/O Standard</b></DIV> <DIV align="center">
Page: XC4VSX35-10FFG668C - Supported Differential IO Standards
The following table lists the differential I/O standards supported by the XC4VSX35-10FFG668C device. Table 1. Supported differential I/O standards. <DIV align="center"><b>I/O Standard</b></DIV> <DIV align="center"><b>Description</b></DIV> BLVDS_25 Bus Low
Page: XC4VSX35-10FFG668C - Supported Single-Ended DCI IO Standards
The following table lists the single-ended DCI (Digitally Controlled Impedance) I/O standards supported by the XC4VSX35-10FFG668C device. Table 1. Supported single-ended DCI I/O standards. <DIV align="center"><b>I/O Standard</b></DIV> <DIV align="center">
Page: XC4VSX35-10FFG668C - Supported Single-Ended IO Standards
The following table lists the single-ended I/O standards supported by the XC4VSX35-10FFG668C device. Table 1. Supported single-ended I/O standards. <DIV align="center"><b>I/O Standard</b></DIV> <DIV align="center"><b>Description</b></DIV> GTL Gunning Tran
Page: Xilinx Configuration Device - Accessing Configuration Device Information
To access information for a physical device, from the Devices view choose the Browse Physical Devices command from the main Tools menu. The Browse Physical Devices dialog will appear, as illustrated in Figure 1. Figure 1. Browsing physical devices for use
Page: Xilinx Configuration Device - Downloading the Configuration File
The configuration for a Xilinx configuration (PROM) device is stored in a PROM file, using the Intel MCS-86 format. This is an ASCII hex file with extension .mcs. To download the new configuration, right-click on the icon for the PROM in the Hard Devices
Page: Xilinx Configuration Device - Erasing the Configuration Device
Before programming the configuration device, it is a good idea to clear its memory first. To do this, right-click on its icon in the Hard Devices chain and choose Reset Hard Device from the pop-up menu. Figure 1. Flushing the configuration PROM device. Th
Page: Xilinx Configuration Device - Generating the Configuration File
Firstly, ensure that the required FPGA project is open in the Projects panel. Open the Devices view, if not already open. Ensure that the Live option is enabled as this enables the auto-board-recognition system. The Hard Devices chainwill display any phys
Page: Xilinx Constraints Entry
Altium Designer's FPGA design environment supports a range of constraints that are device independent. However, since not all FPGA families share the same technology there are also vendor constraints that can be used. The Xilinx tools support a range of c
Page: Xilinx MicroBlaze
Figure 1. MicroBlaze 32-bit processor. The MicroBlaze is a 32-bit Wishbone-compatible RISC processor, for use in FPGA designs targeting supported Xilinx Spartan® or Virtex® families of physical FPGA devices.   Altium Designer currently supports use of the
Page: Xilinx Place and Route Tools Configuration
The place and route tools are all accessed and configured from the Build stage of the Process Flow associated to the target physical device in the Devices view. To enable and display the Process Flow when the target device is a Xilinx FPGA you must: Have
Page: Xilinx PowerPC (PPC405A)
Figure 1. PPC405A 32-bit processor. The PPC405A is a 32-bit Wishbone-compatible RISC processor, for use in FPGA designs targeting the Xilinx® Virtex®-II Pro family of physical FPGA devices. Although placed in an Altium Designer-based FPGA project as a PPC
Page: Xilinx XST Synthesizer Configuration
The system includes a powerful built-in synthesis engine, which is used by default. It also supports use of the Xilinx XST synthesizer within the design environment. To enable an FPGA project to utilize this synthesis tool the project synthesis option mus
Page: Xspice Netlist Output Options
XSpice output options are set up in the *Analyses Setup* dialog. Configuring XSpice Netlist Output Options XSpice output options are set up in the Analyses Setup dialog. Content and Use The Analyses Setup dialog enables you to define the various analyses

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