Altium Designer supports a number of different kinds of projects. Below is a brief description of each.
The set of design documents required to manufacture a printed circuit board.
The electronic circuit is captured as a schematic, built up from libraries of component symbols which are placed and wired together. The design is transferred to the PCB editor where each component is instantiated as a footprint (pattern) and the circuit wiring becomes point-to-point connection lines. A shape for the final PCB is defined, along with the physical layers the board will include. Design rules specify the layout requirements, such as routing widths and clearance. The components are positioned within the board shape and the connection lines are then replaced by routing, either manually or automatically. When the design is complete, standard format output files are generated which can be used to fabricate the blank board, configure an assembly machine, and so on.
The set of design documents that can be processed to program a Field Programmable Gate Array.
The design is captured using schematics and/or HDL code (VHDL or Verilog). Constraint files are added to the project to specify design requirements such as the target device, internal net-to-device pin mapping, net frequency requirements, clock pin allocations, and so on. Design synthesis translates the source data into a low-level gate form, in a standard file format known as EDIF. Device vendor tools then process the EDIF data and attempt to place and route the design in such a way that it will fit in the specified target device, producing a device program file if successful. The design can then be implemented in the target device fitted to a suitable development board and the design can be tested.
The set of design documents required to produce a software application that can be embedded with its executing processor in an electronic product.
The source of the design is captured in C and/or assembly language. When coding is complete, all source files are compiled into assembly language. The assembler then converts them into machine language (object code). The object files are then linked together and mapped into the specified memory space, producing a single, target-ready output file.
The set of design documents required to produce an EDIF representation (model) of a functional component that can be implemented in an FPGA.
The design is captured using schematics and/or HDL code (VHDL or Verilog). Constraint files are added to the project to specify the supported target device(s). Design synthesis translates the source data into a low-level gate form, in a standard file format known as EDIF. A component symbol is drawn to represent the component on a schematic sheet, which then references its EDIF description.
(*.LibPkg) & (*.IntLib)
The set of design documents required to produce an integrated library.
Schematic symbols are drawn in a library editor, and model references defined. Referenced models can include PCB footprints, circuit simulation models, signal integrity models and three-dimensional mechanical models. Files that contain the models are added to the Integrated Library Package (*.LibPkg), or search paths are defined to identify their location. The source schematic symbol libraries and required models are then compiled into a single file, referred to as an Integrated Library.
A set of design documents that stores one or more Altium Designer scripts.
A set of instructions that are interpreted whenever a script is executed in Altium Designer. The scripts are written and debugged in the same environment. There are two types of scripts - script units and script forms. A Script unit can use the DXP Application Programming Interface (API) to modify design objects on a design document. A script form hosts controls, as well as using the DXP API to a provide script dialog that act on design documents open in Altium Designer.