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  1. WB_I2S - Configurable Wishbone Audio Streaming Controller

    Figure 1. WB_I2S - Configurable Wishbone Audio Streaming Controller. The Configurable ... Operational Overview Block Diagram Accessible Internal Registers Interrupt Generation ...

    admin - 11/06/2013 - 09:09

  2. WB_I2S - Configurable Wishbone Audio Streaming Controller

    Figure 1. WB_I2S - Configurable Wishbone Audio Streaming Controller. The Configurable ... Operational Overview Block Diagram Accessible Internal Registers Interrupt Generation ...

    admin - 09/13/2017 - 15:32

  3. WB_I2S - Accessible Internal Registers

    ... The following sections detail the internal registers for the WB_I2S Controller that can be accessed from the host processor. Control ... watermark cpen - prescaler Table 2. The CONTROL register ...

    admin - 11/06/2013 - 09:09

  4. WB_I2S - Accessible Internal Registers

    ... The following sections detail the internal registers for the WB_I2S Controller that can be accessed from the host processor. Control ... watermark cpen - prescaler Table 2. The CONTROL register ...

    admin - 09/13/2017 - 15:32

  5. WB_I2S - Block Diagram

    Figure 1 shows a high-level block diagram for the WB_I2S component. Figure 1. ... WB_I2S that can be accessed from the host processor, see Accessible Internal Registers . ...

    admin - 11/06/2013 - 09:09

  6. WB_I2S - Block Diagram

    Figure 1 shows a high-level block diagram for the WB_I2S component. Figure 1. ... WB_I2S that can be accessed from the host processor, see Accessible Internal Registers . ...

    admin - 09/13/2017 - 15:32

  7. WB_I2S - Host to Controller Communications

    Communications between a 32-bit host processor and the WB_I2S Controller are carried out over a standard Wishbone bus interface. For a ... Host and Controller for writing to/reading from the accessible internal registers , see Wishbone Communications - 32-bit ...

    admin - 11/06/2013 - 09:09

  8. WB_I2S - Host to Controller Communications

    Communications between a 32-bit host processor and the WB_I2S Controller are carried out over a standard Wishbone bus interface. For a ... Host and Controller for writing to/reading from the accessible internal registers , see Wishbone Communications - 32-bit ...

    admin - 09/13/2017 - 15:32

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