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WB_IRRC - Wishbone Infrared Remote Control Codec
Figure 1. WB_IRRC - Wishbone Infrared Remote Control Codec. The Infrared Remote Control ... Operational Overview Block Diagram Accessible Internal Registers Interrupts Host to ...
admin - 11/06/2013 - 09:09
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WB_IRRC - Wishbone Infrared Remote Control Codec
Figure 1. WB_IRRC - Wishbone Infrared Remote Control Codec. The Infrared Remote Control ... Operational Overview Block Diagram Accessible Internal Registers Interrupts Host to ...
admin - 09/13/2017 - 15:32
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WB_IRRC - Accessible Internal Registers
... The following sections detail the internal registers for the WB_IRRC, accessible from the host processor. Clock Divider Register ... FFFF_FFFFh This register is used to hold a 24-bit value, required to generate the modulating carrier clock frequency used in ...
admin - 11/06/2013 - 09:09
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WB_IRRC - Accessible Internal Registers
... The following sections detail the internal registers for the WB_IRRC, accessible from the host processor. Clock Divider Register ... FFFF_FFFFh This register is used to hold a 24-bit value, required to generate the modulating carrier clock frequency used in ...
admin - 09/13/2017 - 15:32
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WB_IRRC - Block Diagram
Figure 1 shows a high-level block diagram for the WB_IRRC component. Figure 1. ... WB_IRRC that can be accessed from the host processor, see Accessible Internal Registers . ...
admin - 11/06/2013 - 09:09
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WB_IRRC - Block Diagram
Figure 1 shows a high-level block diagram for the WB_IRRC component. Figure 1. ... WB_IRRC that can be accessed from the host processor, see Accessible Internal Registers . ...
admin - 09/13/2017 - 15:32
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WB_IRRC - Host to Controller Communications
Communications between a 32-bit host processor and the WB_IRRC Controller are carried out over a standard Wishbone bus interface. For ... Host and Controller for writing to/reading from the accessible internal registers , see Wishbone Communications - 32-bit ...
admin - 11/06/2013 - 09:09
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WB_IRRC - Host to Controller Communications
Communications between a 32-bit host processor and the WB_IRRC Controller are carried out over a standard Wishbone bus interface. For ... Host and Controller for writing to/reading from the accessible internal registers , see Wishbone Communications - 32-bit ...
admin - 09/13/2017 - 15:32