The MicroBlaze is a 32-bit Wishbone-compatible RISC processor, for use in FPGA designs targeting supported Xilinx Spartan® or Virtex® families of physical FPGA devices.
Although placed in an Altium Designer-based FPGA project as a MicroBlaze, this is essentially a Wishbone-compliant wrapper that allows use of the 'soft' MicroBlaze processor core.
All instructions are 32-bits wide and most execute in a single clock cycle. In addition to fast register access, the MicroBlaze features a user-definable amount of zero-wait state block RAM, with true dual-port access.
Only designs targeting supported Spartan or Virtex FPGA devices may make use of the processor. Should you wish the freedom of a both a device and FPGA Vendor-independent 32-bit system hardware platform, use the available TSK3000A 32-bit RISC processor.
- 3-stage pipelined RISC processor
- Internal Harvard architecture
- Supports on-chip block RAM and/or external memory
- 4GByte address space
- Wishbone I/O and memory ports for simplified peripheral connection
- Full Viper-based software development tool chain – C compiler/assembler/source-level debugger/profiler
- C-code compatible with other Altium Designer 8-bit and 32-bit Wishbone-compliant processor cores, for easy design migration.
From an OpenBus System document, the MicroBlaze processor can be found in the Processors region of the OpenBus Palette panel.
From a schematic document, the MicroBlaze processor can be found in the FPGA 32-Bit Processors integrated library (
FPGA 32-Bit Processors.IntLib), located in the
\Library\Fpga folder of the installation.
32-bit Processor Fundamentals
Working with the MicroBlaze
For detailed information about the hardware and functionality of the MicroBlaze processor, including internal registers, refer to the MicroBlaze Processor Reference Guide, available from www.xilinx.com/microblaze. The MicroBlaze Instruction Set Architecture section of this guide provides detailed information with respect to the processor's instruction set, including instruction encoding and an alphabetical listing of all instructions by mnemonic.