WB_UART8_V2 - Wishbone Serial Communications Port (Version 2)

Figure 1. WB_UART8_V2 - Wishbone Serial Communications Port (Version 2).

Serial ports on embedded systems often provide a 2-wire communication channel only. The Wishbone Serial Communications Port component (WB_UART8_V2) facilitates serial communication with hardware handshake and FIFO buffers.

The WB_UART8_V2 can be used with any of the Wishbone-compliant processors available in Altium Designer.

Features at-a-glance

• 8-bit UART (fixed to no parity, 8 data bits and 1 stop bit)

• Full Duplex

• 16-byte FIFO input buffer

• 8-byte FIFO output buffer

• Automatic RTS/CTS hardware-controlled handshake, with user-definable watermark levels

• Dedicated, high precision internal Baud rate generator

• Ability to specify a transmitter inter-character delay

• Support for transmit and receive BREAK conditions

• Wishbone-compliant

Availability

From an OpenBus System document, the Serial Communications component can be found in the Peripherals region of the OpenBus Palette panel.

From a schematic document, the WB_UART8_V2 component can be found in the FPGA Peripherals (Wishbone) integrated library (FPGA Peripherals (Wishbone).IntLib), located in the \Library\Fpga folder of the installation.

Designing with the WB_UART8_V2

Use the following links to explore use of the WB_UART8_V2 in more detail: