Via stitching is a technique used to tie together larger copper areas on different layers, in effect creating a strong vertical connection through the board structure, helping maintain a low impedance and short return loops. In RF designs stitching is used in combination with guard rings to create a via wall, helping create an electromagnetically 'quiet' PCB. Via stitching can also be used to tie areas of copper that might otherwise be isolated from their net, to that net.
An area of the board where stitching vias have been added.
Adding Stitching Vias to a Net
Select the Tools » Via Stitching » Auto Stitch Net command to automatically add stitching vias to the specified net across the board.
Via stitching is run as a post-process, filling free areas of copper with stitching vias. For via stitching to occur, there must be overlapping regions of copper that are attached to the specified net, on different layers. Supported regions of copper include Fills, Polygons and Power Planes.
Select the Tools » Via Stitching » Auto Stitch Net command from the menus to add stitching vias to a specific net. The Add Stitching to Net dialog will open, where the Stitching Parameters and Via Style are specified. Using the selected net, the stitching algorithm identifies all Fills, Polygons and Power Planes attached to that net and attempts to connect them through the board, using the specified via and stitching pattern.
The via stitching algorithm treats Polygons, Fills and Planes in the following way:
- Polygons and Fills that are on the same net are stitched wherever they overlap on different layers. If there are Polygons or Fills on other nets that are overlapping within that area (on another layer), stitching is not applied in that region. Overlapping Plane regions on other nets are passed through.
- Overlapping Plane regions on the target net are always stitched, regardless of the presence of Plane regions (on another layer) attached to other nets. Rule 1 above applies if there are Polygons or Fills overlapping in the same region.
The stitching parameters control the stitching vias' placement pattern, and their clearance from other-net and same-net objects.
- Net - Select the Net to be used for stitching first as this effects the behavior of other options, such as clicking the Load values from Routing Via Style Rule button.
- Grid - the distance between the center of adjacent stitching vias. Stitching vias will not be placed in violation of applicable design rules, if a potential via site would result in a violation that site is skipped.
- Stagger alternate rows - alternate rows of stitching vias are offset by half of the Grid value.
Clearance from Same-net Objects and Edges
There are 2 ways of controlling the clearance of stitching vias, to vias and pads on the same net. Either the applicable Clearance design rule is used, or the Default Via/Pad Clearance specified here in the dialog is used. If a rule exists, then the tighter of these 2 settings is used. These options behave as follows:
- Default Via/Pad Clearance - stitching vias are only placed on potential stitching sites if this much clearance exists. Since potential stitching sites are determined by the stitching grid, it is likely they will be further than apart than this setting.
- Create New Clearance Rule - a stitching via -versus- other via/pad design rule is created when this button is clicked. This rule setting is used to ensure a potential stitching site is valid. When the button is clicked the PCB Rules and Constraints Editor opens, so that the rule Constraints can be set. Note that the rule is named and scoped to target the net selected in the Add Stitching to Net dialog.
- Edit Clearance Rule - this will be the button text if an applicable design rule already exists. Click to change the rule Constraint settings.
- Min Boundary Clearance - stitching vias are only placed on potential stitching sites if this much clearance exists to the edge of Polygon/Fill/Plane regions.
Clearance from Other-net Objects
The clearance from a stitching via to objects on other nets is controlled by the applicable clearance design rule. A stitching via will not be placed on a potential stitching site if it will violate the applicable design rule.
The stitching Via Style can be configured manually in the Add Stitching to Net dialog, or imported from the applicable Routing Via Style design rule by clicking the Load values from Routing Via Style Rule button. Clicking this button will load the Preferred rule settings.
- Once stitching is complete, you will need to re-pour the polygons if the applicable Polygon Connect Style design rule specifies a relief connection style.
- Each set of stitching vias are added to a union. The set can be removed by running the Tools » Via Stitching » Remove Via Stitching Group command, then clicking on any via in the group.