The following table lists the differential I/O standards supported by the XC3S1500-4FG676C device.

Table 1. Supported differential I/O standards.
<DIV align="center"><b>I/O Standard</b></DIV>
 
<DIV align="center"><b>Description</b></DIV>

BLVDS_25

Bus Low-Voltage Differential Signaling (2.5V)

DIFF_HSTL_II_18

Differential High-Speed Transceiver Logic (1.8V) Class II

DIFF_SSTL2_II

Differential Stub Series Terminated Logic (2.5V) Class II

LDT_25

Lightning Data Transport (2.5V)

LVDS_25

Low-Voltage Differential Signaling (2.5V)

LVDSEXT_25

Extended Low-Voltage Differential Signaling (2.5V)

LVPECL_25

Low-Voltage Positive Emitter-Coupled Logic (2.5V)

RSDS_25

Reduced Swing Differential Signaling (2.5V)

Notes

DCI (Digitally Controlled Impedance) option is available in each case, with the exception of the following:

For more detailed information, refer to the Spartan-3 Generation FPGA User Guide (ug331.pdf), available at www.xilinx.com.